<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: RT1060 HyperRAM+QSPINAND in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/RT1060-HyperRAM-QSPINAND/m-p/1413420#M187002</link>
    <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/193658"&gt;@RichardY&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; RT1060 FlexSPI supports NAND, looks it is wrongly updated RM. We will fix it in newer revision.&lt;BR /&gt;&lt;BR /&gt;Note: &lt;BR /&gt;&amp;nbsp;&amp;nbsp; RT10xx does only support boot to internal SRAMs (xTCM/OCRAMs), external RAM not really supported. It will require cooperation of DCD + application code. DCD can be used to initialize external RAM memory interface (FlexSPI) and application startup can copy the code from non-volitile memory (FelxSPI dedicated QSPI flash) to external RAM, and then execute code.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
    <pubDate>Tue, 15 Feb 2022 04:58:19 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2022-02-15T04:58:19Z</dc:date>
    <item>
      <title>RT1060 HyperRAM+QSPINAND</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1060-HyperRAM-QSPINAND/m-p/1402870#M186098</link>
      <description>&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;I am developing my custom board. I am running out of I/Os on RT1060. I realized that I will be able to save I/Os by using the serial RAM (HyperRAM) instead of parallel SDRAM. But we are not sure if this would work&lt;/P&gt;&lt;P&gt;My Configuration:&lt;/P&gt;&lt;P&gt;a. QSPINAND on flexspi1 to store the binary.&lt;/P&gt;&lt;P&gt;b. HyperRAM on flexspi2. Executing the binary from here and also put the stack and heap here.&lt;/P&gt;&lt;P&gt;I have a few questions.&lt;/P&gt;&lt;P&gt;1. Is it possible to execute binary from HyperRAM and also put stack and heap on it? As NXP also provided a example of polling transfer to HyperRAM and it is difficult for us to try out this configuration on any of the evaluation board.&lt;/P&gt;&lt;P&gt;2. We realized that HyperRAM/flexspi needs to be configured before using. Would be able to easily debug the code on HyperRAM? or does MCU-link support configuring the HyperRAM/flexspi before downloading &amp;amp; executing the binary from HyperRAM? We are currently using MCUXpresso.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks and regards,&lt;/P&gt;&lt;P&gt;Richard&lt;/P&gt;</description>
      <pubDate>Thu, 20 Jan 2022 21:12:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1060-HyperRAM-QSPINAND/m-p/1402870#M186098</guid>
      <dc:creator>RichardY</dc:creator>
      <dc:date>2022-01-20T21:12:04Z</dc:date>
    </item>
    <item>
      <title>Re: RT1060 HyperRAM+QSPINAND</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1060-HyperRAM-QSPINAND/m-p/1403928#M186194</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/193658"&gt;@RichardY&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; I have some doubts if i.MX RT1060 supports Serial NAND and HyperBus. &lt;BR /&gt;According the i.MX RT1060 Reference Manual (RM) FlexSPI supports (only) &lt;BR /&gt;Serial NOR Flash or other device with similar SPI protocol as Serial NOR Flash.&lt;BR /&gt;Note, i.MX RT1050 RM and RT1170 RM state about Serial NAND Flash&lt;BR /&gt;and HyperBus using explicitly.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Mon, 24 Jan 2022 11:06:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1060-HyperRAM-QSPINAND/m-p/1403928#M186194</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2022-01-24T11:06:35Z</dc:date>
    </item>
    <item>
      <title>Re: RT1060 HyperRAM+QSPINAND</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1060-HyperRAM-QSPINAND/m-p/1404168#M186214</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/1941"&gt;@Yuri&lt;/a&gt;,&lt;/P&gt;&lt;P&gt;Thank you for your prompt reply.&lt;/P&gt;&lt;P&gt;We were planning to use RT1050, but we run out of the I/Os so we are considering RT1060 to use serial RAM and flash at the same time. I realized that Hyper bus example is not given in the reference manual of RT1060. However, our configuration is based on section 3.3.1 in&amp;nbsp;AN12240&amp;nbsp;&lt;A href="https://www.nxp.com/docs/en/application-note/AN12240.pdf" target="_blank"&gt;Enhanced Features in i.MX RT1060 (nxp.com)&lt;/A&gt;.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="RichardY_1-1643058068597.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/168690i2422A01FBD300851/image-size/medium?v=v2&amp;amp;px=400" role="button" title="RichardY_1-1643058068597.png" alt="RichardY_1-1643058068597.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Would you be able to check with your engineers on this configuration? Would NXP recommend this configuration?&amp;nbsp;&lt;/P&gt;&lt;P&gt;a. QSPINAND on flexspi1 to store the binary.&lt;/P&gt;&lt;P&gt;b. HyperRAM on flexspi2. Executing the binary from here and also put the stack and heap here.&lt;/P&gt;&lt;P&gt;Thanks and regards,&lt;/P&gt;&lt;P&gt;Richard&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 24 Jan 2022 21:13:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1060-HyperRAM-QSPINAND/m-p/1404168#M186214</guid>
      <dc:creator>RichardY</dc:creator>
      <dc:date>2022-01-24T21:13:14Z</dc:date>
    </item>
    <item>
      <title>Re: RT1060 HyperRAM+QSPINAND</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1060-HyperRAM-QSPINAND/m-p/1413420#M187002</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/193658"&gt;@RichardY&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; RT1060 FlexSPI supports NAND, looks it is wrongly updated RM. We will fix it in newer revision.&lt;BR /&gt;&lt;BR /&gt;Note: &lt;BR /&gt;&amp;nbsp;&amp;nbsp; RT10xx does only support boot to internal SRAMs (xTCM/OCRAMs), external RAM not really supported. It will require cooperation of DCD + application code. DCD can be used to initialize external RAM memory interface (FlexSPI) and application startup can copy the code from non-volitile memory (FelxSPI dedicated QSPI flash) to external RAM, and then execute code.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Tue, 15 Feb 2022 04:58:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1060-HyperRAM-QSPINAND/m-p/1413420#M187002</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2022-02-15T04:58:19Z</dc:date>
    </item>
  </channel>
</rss>

