topic Re: iMX8M Nano: SNVS LPGPR in i.MX Processors

iMX8M Nano: SNVS LPGPR

wooosaiiii — Fri, 15 Oct 2021 07:19:45 GMT

Hi all,

I am trying to write a value to SNVS LPGPR0 register on i.MX8M Nano SoC.

However register doesn't accept my values, in fact they always stay at 0x00000000 (default).

Here is my test procedure:

U-Boot > mw 0x30370068 0xDEADBEEF U-Boot > md 0x30370068 1 30370068: 00000000 .... U-Boot >

Where address 0x30370068 is the address of SNVS_LP General Purpose Register 0 (legacy alias) (LPGPR0_legacy_alias).

The same can be observed if using registers "SNVS_LP General Purpose Registers 0 .. 3 (LPGPR0 - LPGPR3)":

U-Boot > mw 0x30370090 0xDEADBEEF U-Boot > mw 0x30370094 0xDEADBEEF U-Boot > mw 0x30370098 0xDEADBEEF U-Boot > mw 0x3037009C 0xDEADBEEF U-Boot > md 0x30370090 4 30370090: 00000000 00000000 00000000 00000000 ................ U-Boot >

What am I missing?

The same works like a charm on i.MX6UL board which should have the same SNVS controller?

ps.: here is a dump of entire controller registers:

30370000: 00000001 00002020 00000000 00000000 .... .......... 30370010: 00000000 8000bd00 80000000 00000000 ................ 30370020: 00000000 00000000 00000000 00000000 ................ 30370030: 00000000 00000000 00000020 00000000 ........ ....... 30370040: 00000000 00000000 00000000 00000008 ................ 30370050: 00000000 00000000 00000000 00000000 ................ 30370060: 00000000 00000000 00000000 00000000 ................ 30370070: 00000000 00000000 00000000 00000000 ................ 30370080: 00000000 00000000 00000000 00000000 ................ 30370090: 00000000 00000000 00000000 00000000 ................

Re: iMX8M Nano: SNVS LPGPR

igorpadykov — Fri, 15 Oct 2021 13:27:32 GMT

Hi Primoz

recommended to use SNVS LPGPR alias registers @ 0x90 - 0x9C.

Best regards
igor

Re: iMX8M Nano: SNVS LPGPR

wooosaiiii — Mon, 18 Oct 2021 06:30:30 GMT

Hi @igorpadykov ,

I tried using registers SNVS LPGPR alias registers @ 0x90 - 0x9C, see:

The same can be observed if using registers "SNVS_LP General Purpose Registers 0 .. 3 (LPGPR0 - LPGPR3)":

U-Boot > mw 0x30370090 0xDEADBEEF 
U-Boot > mw 0x30370094 0xDEADBEEF
U-Boot > mw 0x30370098 0xDEADBEEF
U-Boot > mw 0x3037009C 0xDEADBEEF
U-Boot > md 0x30370090 4         
30370090: 00000000 00000000 00000000 00000000    ................
U-Boot >

without success...

RM says that those registers cannot be programmed when:

When GPR_SL or GPR_HL bit is set, the register cannot be programmed.

Can you tell which register has those two bits as we cannot find them in the RM?

Thanks

Re: iMX8M Nano: SNVS LPGPR

igorpadykov — Mon, 18 Oct 2021 09:35:44 GMT

>Can you tell which register has those two bits as we cannot find them in the RM?

they can be found in SNVS_HP Lock Register (HPLR), SNVS_LP Lock Register (LPLR) described in

Security Reference Manual for i.MX 8M Nano Applications Processor

Best regards
igor

Re: iMX8M Nano: SNVS LPGPR

M_J — Sun, 31 Oct 2021 18:30:34 GMT

Hi @wooosaiiii ,
Have you found solution for your issue?
We are facing the same problem on i.MX8M

Re: iMX8M Nano: SNVS LPGPR

wooosaiiii — Tue, 02 Nov 2021 05:48:57 GMT

Yes, we have solved the issue.

Basically, you need to write the init value and clear the low-voltage event:

#define IMX8M_SNVS_LPLVDR (0x30370064) #define IMX8M_SNVS_LPSR (0x3037004C) #define IMX8M_SNVS_LPLVDR_INIT_VAL (0x41736166) #define IMX8M_SNVS_LPSR_CLEAR_EVENT (0x00000008) /** * First write initialisation value to SNVS LPLVDR Digital Low-Voltage * Detector Register and then clear the Low-Voltage Event Record in the * SNVS LPSR Status Register */ *(volatile uint32_t *) IMX8M_SNVS_LPLVDR = IMX8M_SNVS_LPLVDR_INIT_VAL; *(volatile uint32_t *) IMX8M_SNVS_LPSR = IMX8M_SNVS_LPSR_CLEAR_EVENT;

Last but not least, if you're using HAB features, you will need to enable access to privileged registers.

Re: iMX8M Nano: SNVS LPGPR

wouher — Wed, 19 Jan 2022 13:35:21 GMT

Could you comment on how you enabled access to privileged registers when using HAB features?

Because I can write to e.g. the LPGPR using the method described in this thread, but only when HAB is disabled.

Re: iMX8M Nano: SNVS LPGPR

M_J — Wed, 19 Jan 2022 14:10:50 GMT

We haven't done anything special, just write a value under casted GPR register.

Re: iMX8M Nano: SNVS LPGPR

wooosaiiii — Thu, 20 Jan 2022 05:02:56 GMT

Call init_snvs() in arch_cpu_init().

Use init_snvs() from i.MX7 arch.

Re: iMX8M Nano: SNVS LPGPR

wouher — Thu, 20 Jan 2022 08:25:34 GMT

Thanks, that's it