Dual channel split mode register configuration

小李 — Thu, 13 Jan 2022 03:54:35 GMT

Recently, I have been learning LVDS dual-channel split mode display. Through learning, I found that the kernel stage has been well adapted, and the screen parameters can be displayed directly after adjustment. In the Uboot stage, only one channel is opened, and the second channel can also be displayed normally.

The following problems occur during configuration and thinking:

1. According to the manual, in split mode, both LVDS channels should use the same DI. In kernel driver, SPL0 is used, so there is no problem in gPR2 register setting, but gPR3 LVDS0_MUX_CTL and LVDS1_MUX_CTL are different. The DI ports of two different IPUs were used, so I was a bit confused about what this pathway was like.

我对寄存器的值做过一些修改测试，没有找到什么规律

What should I do, please

Re: Dual channel split mode register configuration

igorpadykov — Thu, 13 Jan 2022 06:28:33 GMT

for dual channel example one can look at below patch

https://community.nxp.com/t5/i-MX-Processors/imx6q-and-lvds/m-p/391391#525359

Best regards
igor

i.MX ProcessorsのトピックDual channel split mode register configuration

Dual channel split mode register configuration

Re: Dual channel split mode register configuration