i.MX ProcessorsのトピックRe: How to use PCIE internal PLL on imx8mplus platform .

How to use PCIE internal PLL on imx8mplus platform .

t2865k5 — Fri, 24 Dec 2021 08:59:31 GMT

Dear NXP ,

HW : srg_imx8mplus

SW : kernel version : 5.10.9

Because srg_imx8mplus PCIE is not connected to an oscillator, I modified the content of imx8mp-evk.dts as follows:

ext_osc = <0>;

I connected the PCIE device to the srg_imx8mplus platform ,and ran the lspci command. I did not see any message.

I check the imx8mp_pcie0.log . The message is as follows:

.....

PLL REF_CLK is used!.

....

I don’t see the PCIE Link up message .

Could you tell me how to use PCIE internal PLL on imx8mplus platform ?

t2865k5_0-1640336146450.png

Re: How to use PCIE internal PLL on imx8mplus platform .

igorpadykov — Fri, 24 Dec 2021 09:28:26 GMT

Hi Albert

in general for internal clock only ext_osc = <0>; change is needed.

May be recommended to check clock with oscilloscope and try with several pcie cards.

Best regards
igor

Re: How to use PCIE internal PLL on imx8mplus platform .

t2865k5 — Mon, 03 Jan 2022 02:48:11 GMT

Dear Igorpadykov ,

I hope to simplify the problem. I measured the signal on the PCIE_CLKP pin, and there is no oscillation waveform.

How to solve this problem ?

Re: How to use PCIE internal PLL on imx8mplus platform .

igorpadykov — Mon, 03 Jan 2022 05:50:30 GMT

to narrow down issue if it is caused by hardware or software, please try to reproduce

issue on i.MX8M Plus EVK board.

Best regards
igor

Re: How to use PCIE internal PLL on imx8mplus platform .

t2865k5 — Tue, 04 Jan 2022 07:30:14 GMT

Hi Igor ,

(1) imx8mplus platform: imx8mp-evk.dts ext_osc = <0>;
It can measure the PCIE_CLKN waveform
(2) srg_imx8mplus platform: imx8mp-evk.dts ext_osc = <0>;
The PCIE_CLKN waveform can be measured when starting up, and the oscillating waveform will disappear after 5 seconds.
(3) I have a question, in pci-imx6.c:
imx6_pcie_init_phy() {
..
case IMX8MP:
case IMX8MP_EP:
}

IMX8MM: According to the value of imx6_pcie->ext_osc to set
External clock and internal PLL settings. But case IMX8MP : The imx6_pcie->ext_osc variable is not set ,so no matter the value of imx6_pcie->ext_osc is 0 or 1, it will be the output of the external clock. Is my idea correct?

Re: How to use PCIE internal PLL on imx8mplus platform .

igorpadykov — Tue, 04 Jan 2022 07:55:14 GMT

> But case IMX8MP : The imx6_pcie->ext_osc variable is not set ,so no matter the value of >imx6_pcie->ext_osc is 0 or 1, it will be the output of the external clock. Is my idea correct?

please look at (imx6_pcie->ext_osc is 0 or 1 is correctly handled):

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/pci/controller/dwc/pci-imx6.c?h=lf-5.10.y

Best regards
igor

Re: How to use PCIE internal PLL on imx8mplus platform .

t2865k5 — Thu, 06 Jan 2022 06:04:35 GMT

Hi igor ,

srg_imx8mplus platform:
It connects to another board with PCIE device through the connector.
I can't use general PCIE card on the srgimx8mplus platform.

This is the new PCIE board we designed.
I can't confirm that the PCIE board hardware is ok.

I modify device tree: osc = <0>;
When it boot , I measured
the PCIE_CLKN pin ,and it appear oscillating waveform . The oscillating waveform disappear within 2 seconds.
log:
imx6_pcie_host_init
imx6q-pcie 33800000.pcie: invalid resource
imx6q-pcie 33800000.pcie: Phy link never came up

ret = dw_pcie_wait_for_link(pci);

imx6q-pcie 33800000.pcie: ret=0xffffff92
imx6q-pcie 33800000.pcie: failed to initialize host

I have a question: When software set the internal PLL to output PCIE clock, the PCIE device is not connected.
It link fail ,and it will disable PLL clock.
Is my idea right?

Re: How to use PCIE internal PLL on imx8mplus platform .

igorpadykov — Thu, 06 Jan 2022 10:03:41 GMT

yes right.

Best regards
igor

Re: How to use PCIE internal PLL on imx8mplus platform .

emptyfridge — Mon, 08 Jan 2024 12:18:13 GMT

Hi all,

I have exactly the same behavior with imx8mm, try to use internal clk for PCIe. kernel 5.10.

       [    1.652640] imx6q-pcie 33800000.pcie: supply epdev_on not found, using dummy regulator
       [    1.667816] imx6q-pcie 33800000.pcie: PLL REF_CLK is used!.
       [    1.674263] imx6q-pcie 33800000.pcie: PCIe PLL locked after 20 us.
       [    1.683330] imx6q-pcie 33800000.pcie: host bridge /soc@0/pcie@33800000 ranges:
       [    1.690581] imx6q-pcie 33800000.pcie:       IO 0x001ff80000..0x001ff8ffff -> 0x0000000000
       [    1.707443] imx6q-pcie 33800000.pcie:      MEM 0x0018000000..0x001fefffff -> 0x0018000000
       [    1.715803] imx6q-pcie 33800000.pcie: invalid resource
       [    2.730995] imx6q-pcie 33800000.pcie: Phy link never came up
       [    2.736699] imx6q-pcie 33800000.pcie: failed to initialize host
       [    2.742628] imx6q-pcie 33800000.pcie: unable to add pcie port.

what I have in devtree:

pcie0_refclk: pcie0-refclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; ............. pinctrl_pcie0: pcie0grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x41 /* AF9 WAKE */ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x41 /* AGF8 PERST */ >; }; ............ &pcie0{ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio5 5 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_PHY>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <100000000>, <250000000>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_100M>, <&clk IMX8MM_SYS_PLL2_250M>; ext_osc = <0>; status = "okay"; };

Same with the measuring. I can see the clock for about 2 seconds and then it stops.

Is there any new hints for that?