<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: i.MX8 LPDDR REGISTER CONFIG</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8-LPDDR-REGISTER-CONFIG/m-p/1393136#M185178</link>
    <description>&lt;P&gt;Hi Liu&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;is it LPDDR4 or DDR4 part. For DDR4 part it is necessary to enter&lt;BR /&gt;Number of BANK addresses and Number of BANK GROUP addresses&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="1.jpg" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/166463iBB05414199D7B69C/image-size/medium?v=v2&amp;amp;px=400" role="button" title="1.jpg" alt="1.jpg" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;1.jpg&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt; &lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
    <pubDate>Wed, 29 Dec 2021 23:42:10 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2021-12-29T23:42:10Z</dc:date>
    <item>
      <title>i.MX8 LPDDR REGISTER CONFIG</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8-LPDDR-REGISTER-CONFIG/m-p/1391902#M185008</link>
      <description>&lt;P&gt;About Address Map Register:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; DDR4:only 4 banks.I do not know how to set addrmap_bank_b0,addrmap_bank_b1,addrmap_bank_b2 ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 25 Dec 2021 10:55:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8-LPDDR-REGISTER-CONFIG/m-p/1391902#M185008</guid>
      <dc:creator>ldwtail</dc:creator>
      <dc:date>2021-12-25T10:55:40Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8 LPDDR REGISTER CONFIG</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8-LPDDR-REGISTER-CONFIG/m-p/1393136#M185178</link>
      <description>&lt;P&gt;Hi Liu&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;is it LPDDR4 or DDR4 part. For DDR4 part it is necessary to enter&lt;BR /&gt;Number of BANK addresses and Number of BANK GROUP addresses&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="1.jpg" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/166463iBB05414199D7B69C/image-size/medium?v=v2&amp;amp;px=400" role="button" title="1.jpg" alt="1.jpg" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;1.jpg&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt; &lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
      <pubDate>Wed, 29 Dec 2021 23:42:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8-LPDDR-REGISTER-CONFIG/m-p/1393136#M185178</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2021-12-29T23:42:10Z</dc:date>
    </item>
  </channel>
</rss>

