topic Re: SEMC SRAM interface in i.MX Processors

SEMC SRAM interface

ShiXiang — Tue, 07 Dec 2021 10:20:28 GMT

product: I.mxrt 1170 series

For the SRAM write/read in SYNC mode (ADMUX), just wonder is it possible to mask the higher address bit, A[M : 16], means not to use and free up my address pin, so that I can connect them extra GPIOs.

My SRAM application only need A0-15.

Re: SEMC SRAM interface

ShiXiang — Fri, 10 Dec 2021 02:53:32 GMT

Can the software call function/register support on masking or is the software/register adjustable? For masking the higher address bit, A[M : 16], while using SRAM write/read in SYNC mode (ADMUX) . Thank you.

Re: SEMC SRAM interface

ShiXiang — Thu, 16 Dec 2021 01:42:12 GMT

No reply yet, re-post to I.MX RT page.

Please close this question, thank you.

Re: SEMC SRAM interface

art — Fri, 17 Dec 2021 11:22:37 GMT

Yes, it is possible to use upper address pins (A16 and higher) as GPIOs when
SEMC operates in SRAM mode. Just configure these pins as GPIOs in IOMUXC.

Best Regards,
Artur