topic Re: IMX clock domain in i.MX Processors

IMX clock domain

justinfei — Sun, 28 Nov 2021 09:19:47 GMT

When I read the datesheet of IMX8mq about the CCM.

1.I can't understand the clock domain usage and why the same clock have 4 domain setting(for example CCM_PLL_CTRLn has setting1 ~setting3).The 4 domain settings of one clock are working at the same time?

2.What is the usage of PLL domain settings and CCGR domain settings?

em......NXP's datasheets are hard to understand!

Re: IMX clock domain

igorpadykov — Mon, 29 Nov 2021 00:32:25 GMT

for domain usage one can look at description in sect.5.1.5.7 Access control, sect.5.1.6.2 PLL Interface,

sect.5.2.4.2 Low power mode

i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual

Best regards
igor

Re: IMX clock domain

tamotsu — Fri, 21 Jul 2023 07:44:47 GMT

Hi.

I also didn't understand that there are 4 domains.

"3.2.1.1 Features" of Resource Domain COntroller(RDC) in i.MX7D reference manual written as follews.

Assignment of cores, bus masters, peripherals, and memory regions to a resource domain.

Four of these ?

But it dosen't write which one is domain0.