RSTA bit in the uSDHCx_SYS_CTRL register is not self cleared

tomohiroseki — Wed, 24 Nov 2021 06:38:40 GMT

Hi All,
We have a i.MX6ULL custom board and work well until recently, but now facing issue with RSTA bit.

・RSTA bit in the uSDHCx_SYS_CTRL register is not self cleared once in 10~1000 times.
・We have another i.MX6Q custom board, and haven't encountered issue like this.

・Serial Console message
---------------------------------------------------------------------------------------
U-Boot 2017.03-imx_v2017.03_4.9.88_2.0.0_ga (Jul 16 2019 - 16:25:59 +0900)

CPU: Freescale i.MX6ULL rev1.1 at 900MHz
CPU: Commercial temperature grade (0C to 95C) at 48C
Reset cause: POR
Model: xxxxx
Board: xxxxx
DRAM: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
In: serial
Out: serial
Err: serial
switch to partitions #0, OK
mmc1(part 0) is current device
Net: FEC
Normal Boot
Hit any key to stop autoboot: 0
reading zImage
6384280 bytes read in 158 ms (38.5 MiB/s)
Booting from mmc ...
reading imx6ull-xxxxx.dtb
32838 bytes read in 18 ms (1.7 MiB/s)
## Flattened Device Tree blob at 83000000
Booting using the fdt blob at 0x83000000
Using Device Tree in place at 83000000, end 8300b045
Modify /soc/aips-bus@02200000/epdc@0228c000:status disabled
ft_system_setup for mx6

Starting kernel ...

/cpus/cpu@0 missing clock-frequency property
mmc1: Reset 0x1 never completed.
mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
mmc1: sdhci: Sys addr: 0x00000000 | Version: 0x00000002
mmc1: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000001
mmc1: sdhci: Argument: 0x00004fb8 | Trn mode: 0x00000000
mmc1: sdhci: Present: 0x01f88088 | Host ctl: 0x00000020
mmc1: sdhci: Power: 0x00000000 | Blk gap: 0x00000080
mmc1: sdhci: Wake-up: 0x00000008 | Clock: 0x0000003f
mmc1: sdhci: Timeout: 0x0000008c | Int stat: 0x00000000
mmc1: sdhci: Int enab: 0x007f010b | Sig enab: 0x00000000
mmc1: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000302
mmc1: sdhci: Caps: 0x07eb0000 | Caps_1: 0x0000b407
mmc1: sdhci: Cmd: 0x0000113a | Max curr: 0x00ffffff
mmc1: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0xffffffff
mmc1: sdhci: Resp[2]: 0x320f5913 | Resp[3]: 0x00d02f01
mmc1: sdhci: Host ctl2: 0x00000000
mmc1: sdhci: ============================================
mmc1: Reset 0x1 never completed.
mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
mmc1: sdhci: Sys addr: 0x00000000 | Version: 0x00000002
mmc1: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000001
mmc1: sdhci: Argument: 0x00004fb8 | Trn mode: 0x00000000
mmc1: sdhci: Present: 0x01f88088 | Host ctl: 0x00000020
mmc1: sdhci: Power: 0x00000000 | Blk gap: 0x00000080
mmc1: sdhci: Wake-up: 0x00000008 | Clock: 0x0000003f
mmc1: sdhci: Timeout: 0x0000008c | Int stat: 0x00000000
mmc1: sdhci: Int enab: 0x00000000 | Sig enab: 0x00000000
mmc1: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000302
mmc1: sdhci: Caps: 0x07eb0000 | Caps_1: 0x0000b407
mmc1: sdhci: Cmd: 0x0000113a | Max curr: 0x00ffffff
mmc1: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0xffffffff
mmc1: sdhci: Resp[2]: 0x320f5913 | Resp[3]: 0x00d02f01
mmc1: sdhci: Host ctl2: 0x00000000
mmc1: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x00000000
mmc1: sdhci: ============================================
mmc1: Timeout waiting for hardware cmd interrupt.
mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
mmc1: sdhci: Sys addr: 0x00000000 | Version: 0x00000002
mmc1: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000001
mmc1: sdhci: Argument: 0x00000c00 | Trn mode: 0x00000000
mmc1: sdhci: Present: 0x01f88088 | Host ctl: 0x00000001
mmc1: sdhci: Power: 0x00000000 | Blk gap: 0x00000080
mmc1: sdhci: Wake-up: 0x00000008 | Clock: 0x000010af
mmc1: sdhci: Timeout: 0x0000008c | Int stat: 0x00000000
mmc1: sdhci: Int enab: 0x007f1003 | Sig enab: 0x007f1003
mmc1: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000302
mmc1: sdhci: Caps: 0x07eb0000 | Caps_1: 0x0000b407
mmc1: sdhci: Cmd: 0x0000341a | Max curr: 0x00ffffff
mmc1: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0xffffffff
mmc1: sdhci: Resp[2]: 0x320f5913 | Resp[3]: 0x00d02f01
mmc1: sdhci: Host ctl2: 0x00000000
mmc1: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x00000000
mmc1: sdhci: ============================================
mmc1: Reset 0x2 never completed.
mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
mmc1: sdhci: Sys addr: 0x00000000 | Version: 0x00000002
mmc1: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000001
mmc1: sdhci: Argument: 0x00000c00 | Trn mode: 0x00000000
mmc1: sdhci: Present: 0x01f88088 | Host ctl: 0x00000001
mmc1: sdhci: Power: 0x00000000 | Blk gap: 0x00000080
mmc1: sdhci: Wake-up: 0x00000008 | Clock: 0x000010af
mmc1: sdhci: Timeout: 0x0000008c | Int stat: 0x00000000
mmc1: sdhci: Int enab: 0x007f1003 | Sig enab: 0x007f1003
mmc1: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000302
mmc1: sdhci: Caps: 0x07eb0000 | Caps_1: 0x0000b407
mmc1: sdhci: Cmd: 0x0000341a | Max curr: 0x00ffffff
mmc1: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0xffffffff
mmc1: sdhci: Resp[2]: 0x320f5913 | Resp[3]: 0x00d02f01
mmc1: sdhci: Host ctl2: 0x00000000
mmc1: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x00000000
mmc1: sdhci: ============================================
mmc1: Reset 0x4 never completed.

(continue.....)
---------------------------------------------------------------------------------------

・The error occrus at the code below
(linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver)
---------------------------------------------------------------------------------------
void sdhci_reset(struct sdhci_host *host, u8 mask)
{
ktime_t timeout;
sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
if (mask & SDHCI_RESET_ALL) {
host->clock = 0;
/* Reset-all turns off SD Bus Power */
if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
sdhci_runtime_pm_bus_off(host);
}
/* Wait max 100 ms */
timeout = ktime_add_ms(ktime_get(), 100);
/* hw clears the bit when it's done */
while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
if (ktime_after(ktime_get(), timeout)) {
pr_err("%s: Reset 0x%x never completed.\n",
mmc_hostname(host->mmc), (int)mask);
sdhci_dumpregs(host);
return;
}
udelay(10);
---------------------------------------------------------------------------------------

・No effect drivers
https://github.com/torvalds/linux/blob/master/drivers/mmc/host/sdhci.c
https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/mmc/host/sdhci-esdhc-imx.c?h=imx_5.4.70_2.3.0
https://github.com/torvalds/linux/blob/master/drivers/mmc/host/sdhci.c
https://github.com/torvalds/linux/blob/master/drivers/mmc/host/sdhci-esdhc-imx.c

・i.MX 6ULL Reference Manual Rev.1 p4036
-------------------------------------------------------------------------------------------------------
RSTA Software Reset For ALL

This reset effects the entire Host Controller except for the card detection circuit. Register bits of type ROC,
RW, RW1C, RWAC are cleared. During its initialization, the Host Driver shall set this bit to 1 to reset the
uSDHC. The uSDHC shall reset this bit to 0 when the capabilities registers are valid and the Host Driver
can read them. Additional use of Software Reset For All does not affect the value of the Capabilities
registers. After this bit is set, it is recommended that the Host Driver reset the external card and reinitialize
it. After this bit is set, SW should wait for self-clear.
-------------------------------------------------------------------------------------------------------

・We have already checked the post below, but not resolved.
　https://community.nxp.com/t5/i-MX-Processors/RSTA-bit-in-the-uSDHCx-SYS-CTRL-register-gets-stuck/td-p/617103

Could you please help on fixing this?

Re: RSTA bit in the uSDHCx_SYS_CTRL register is not self cleared

igorpadykov — Wed, 01 Dec 2021 06:52:39 GMT

Hi Tomohiro

from team:

--------------------

The suggestions are

1. Check the power supply to sdhc and SD/eMMC card.

2. sdhci_reset may be called from sdhci_add_host or other code, check which code cause the first failure of sdhci_reset.

3. ABA swap test on SD/eMMC card, check if it's card issue.

4. ABA swap test on the mx6ull chip, check if it's board issue.

--------------------

Best regards
igor

Re: RSTA bit in the uSDHCx_SYS_CTRL register is not self cleared

tomohiroseki — Fri, 03 Dec 2021 03:49:09 GMT

HI Team,
Thanks your reply.

A1.
This issue occurs even if without any SD cards.
We measure power supply 3.3V with an oscilloscope and found its ok.
The power supply to sdhc controller of soc is as controlled by Linux driver, and we found any defects yet.

A2.
This issue occurs first time sdhci_add_host called.

A3.
As shown forward, this issue occurs without any SD cards, so this is not a card issue.

A4.
This issue is unstable. One day it occurs once in 10~100 times, but other day it doesn't in 4000 times.
So We assume ABA swap test is not effective.

On Our custom boards, We believe hardware related this issue are only below..

i.MX6ULL chip
eMMC(boot) chip
boad(power supply / signals between 2 chips)

What are the other possible causes?

We afraid this is a sdhc controller issue of soc.
Is there any idea or information of such a errata?

Best Regards,
Tomohiro seki

Re: RSTA bit in the uSDHCx_SYS_CTRL register is not self cleared

igorpadykov — Fri, 03 Dec 2021 06:33:06 GMT

>What are the other possible causes?

it was already answered:

1. Check the power supply to sdhc and SD/eMMC card.

2. sdhci_reset may be called from sdhci_add_host or other code, check which code cause the first failure of sdhci_reset.

3. ABA swap test on SD/eMMC card, check if it's card issue.

4. ABA swap test on the mx6ull chip, check if it's board issue.

>We afraid this is a sdhc controller issue of soc.

it was suggested before : " 4. ABA swap test on the mx6ull chip, check if it's board issue."

Please try it.

>Is there any idea or information of such a errata?

Best regards
igor

topic RSTA bit in the uSDHCx_SYS_CTRL register is not self cleared in i.MX Processors

RSTA bit in the uSDHCx_SYS_CTRL register is not self cleared

Re: RSTA bit in the uSDHCx_SYS_CTRL register is not self cleared

Re: RSTA bit in the uSDHCx_SYS_CTRL register is not self cleared

Re: RSTA bit in the uSDHCx_SYS_CTRL register is not self cleared