i.MX ProcessorsのトピックRe: iMX8MN ECSPI Master multi burst SS_CTL

iMX8MN ECSPI Master multi burst SS_CTL

ycx — Thu, 21 Oct 2021 12:52:05 GMT

Hi,

I try to have a master send multi burst (21) of size 8 bits each on ECSPI1 from cortex M7. I want to keep CS/SS low during the transfer of 21 bursts.

As per reference manual I configure the following :

config->channel           = kECSPI_Channel0;
config->burstLength       = 8;
config->samplePeriodClock = kECSPI_spiClock;
config->baudRate_Bps      = 10000000;
config->chipSelectDelay   = 0;
config->samplePeriod      = 0;
config->txFifoThreshold   = 1;
config->rxFifoThreshold   = 0;
/* Default configuration of channel */
ECSPI_GetDefaultChannelConfig(&config->channelConfig);

config->channelConfig.channelMode = kECSPI_Master;

ECSPI_CONREG_SMC set to 0

ECSPI_CONFIGREG_SS_CTL set to 1

Fill the TxData buffer with ECSPI_MasterTransferNonBlocking and then put ECSPI_CONREG_XCH to 1.

What I see on logic analyzer still has the CS/SS rising between bursts :

What am I missing ?

Thanks.

Re: iMX8MN ECSPI Master multi burst SS_CTL

Yuri — Mon, 25 Oct 2021 05:14:15 GMT

@ycx
Hello,

hope the following clarifies the issue.

https://community.nxp.com/t5/i-MX-Processors/imx8-ecspi-Master-Mode-with-SS-CTL-Control/m-p/984674

Regards,
Yuri.

Re: iMX8MN ECSPI Master multi burst SS_CTL

ycx — Mon, 25 Oct 2021 08:11:58 GMT

Hi Yuri,

It does not help as the issue is not resolved.

In the chip errata I found an entry that looks like my issue :

ERR009535: ECSPI: Burst completion by SS signal in slave mode is not functional.

But specified only for slave mode. Are you sure it is not the case also for master mode ?

Thanks,
Yann

Re: iMX8MN ECSPI Master multi burst SS_CTL

Yuri — Mon, 25 Oct 2021 09:07:09 GMT

@ycx

Yes, ERR009535 is for the SPI slave mode.

For the master mode - It is needed to avoid situations, when FIFO
is underflowed (empty) - then the SS is not negated.

Or - to use a GPIO instead of the SS.

~Yuri.

Re: iMX8MN ECSPI Master multi burst SS_CTL

ycx — Mon, 25 Oct 2021 09:49:07 GMT

Yuri,

FIFO is filled with 21x uint32 before XCH is set to 1, so it is not underflowed after each value is sent and SS should remain negated during sending of these 21 values.

I cannot use GPIO.

Regards,
Yann

Re: iMX8MN ECSPI Master multi burst SS_CTL

Yuri — Tue, 26 Oct 2021 03:12:24 GMT

@ycx
Hello,

please try ECSPIx_CONREG[BURST_LENGTH] = 21 x 32 -1

Regards,
Yuri.

Re: iMX8MN ECSPI Master multi burst SS_CTL

ycx — Tue, 26 Oct 2021 09:22:50 GMT

Still no :

I really tried all the combinations.

Yann

Re: iMX8MN ECSPI Master multi burst SS_CTL

kef2 — Tue, 26 Oct 2021 18:35:29 GMT

I believe @Yuri meant 21*8-1. You want to sent 21 octets, not 21 * 32 bit words. What you see in your last waveform should be SS toggling each 512 bits. 512 bits is eCSPI single burst limit. As well

FIFO is filled with 21x uint32 before XCH is set to 1

You should fill FIFO writing 32bit words (21+(4-1)) / 4 times. First write should include first (21 % 4) bytes, the rest of writes should write next 4 bytes each time.

Or, as it was already suggested, toggle SS from software.

Edit: Sorry, BURST_LEN of ECSPIx_CONREG register should be limited to 512 bytes, not bits. Field limits 0..0xFFF should mean 1..4096 bits, or up to 512 bytes.

Edward

Re: iMX8MN ECSPI Master multi burst SS_CTL

ycx — Wed, 27 Oct 2021 09:16:20 GMT

Hi Edward,

Thank you for your proposition.

Indeed this can be achieve but unfortunately the daisy chained slaves that I access need some wait states in between words which I don't know how to add if burst length is anything other than 8.

Regards,
Yann

Re: iMX8MN ECSPI Master multi burst SS_CTL

Yuri — Wed, 27 Oct 2021 09:35:06 GMT

@kef2
@ycx
Hello,

Note: bytes should be packed into 32-bit FIFO words.

Regards,
Yuri.

Re: iMX8MN ECSPI Master multi burst SS_CTL

kef2 — Wed, 27 Oct 2021 09:38:57 GMT

Hm,

If slaves are slow, then lowering clock rate should help. If indeed you need pause between each burst of 8 bits, then clearly you should toggle SS from software.

Edward