<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックWhat is the PCIe i.MX6 max payload size ?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/What-is-the-PCIe-i-MX6-max-payload-size/m-p/233797#M18163</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the reference manual, it is said at chapter 48.4.4.1.1.2 : "Program your PCI Express system with a larger value of Max_Payload_Size without exceeding CX_MAX_MTU (128)."&lt;/P&gt;&lt;P&gt;I can't find any definition for CX_MAX_MTU but the number in parenthesis sugests that it's value is 128. Right ?&lt;/P&gt;&lt;P&gt;Does this means that the max payload size of PCIe packets is 128 bytes ? If true, this means that one can't trim the max payload size which min value is 128 bytes.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Nicolas&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 16 Sep 2013 12:11:22 GMT</pubDate>
    <dc:creator>NicolasP</dc:creator>
    <dc:date>2013-09-16T12:11:22Z</dc:date>
    <item>
      <title>What is the PCIe i.MX6 max payload size ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-is-the-PCIe-i-MX6-max-payload-size/m-p/233797#M18163</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the reference manual, it is said at chapter 48.4.4.1.1.2 : "Program your PCI Express system with a larger value of Max_Payload_Size without exceeding CX_MAX_MTU (128)."&lt;/P&gt;&lt;P&gt;I can't find any definition for CX_MAX_MTU but the number in parenthesis sugests that it's value is 128. Right ?&lt;/P&gt;&lt;P&gt;Does this means that the max payload size of PCIe packets is 128 bytes ? If true, this means that one can't trim the max payload size which min value is 128 bytes.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Nicolas&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Sep 2013 12:11:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-is-the-PCIe-i-MX6-max-payload-size/m-p/233797#M18163</guid>
      <dc:creator>NicolasP</dc:creator>
      <dc:date>2013-09-16T12:11:22Z</dc:date>
    </item>
    <item>
      <title>Re: What is the PCIe i.MX6 max payload size ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-is-the-PCIe-i-MX6-max-payload-size/m-p/233798#M18164</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;From Mark Middleton :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; There are several parameters which sound like they can be set by the user through registers, &lt;/P&gt;&lt;P&gt;but are actually parameters that the core design engineer sets when designing the core into silicon. &lt;/P&gt;&lt;P&gt;Unfortunately, that means that these parameters cannot be changed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Three parameters in particular are:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;CX_MAX_MTU = 128&lt;/P&gt;&lt;P&gt;CC_SLV_MTU = 128&lt;/P&gt;&lt;P&gt;CC_MSTR_BURST_LEN = 16&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; If these values are exceeded in the application software, then the core starts to decompose messages, &lt;/P&gt;&lt;P&gt;which will affect throughput. The reason the core will not work with larger values is because the buffers and &lt;/P&gt;&lt;P&gt;memory space needed to support the larger values are not built into the core.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 03 Oct 2013 05:49:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-is-the-PCIe-i-MX6-max-payload-size/m-p/233798#M18164</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2013-10-03T05:49:22Z</dc:date>
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    <item>
      <title>Re: What is the PCIe i.MX6 max payload size ?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-is-the-PCIe-i-MX6-max-payload-size/m-p/233799#M18165</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your answer. &lt;/P&gt;&lt;P&gt;That's what I thought. One can not change max payload size. It is fixed to 128 bytes.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Nicolas&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 07 Oct 2013 07:03:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-is-the-PCIe-i-MX6-max-payload-size/m-p/233799#M18165</guid>
      <dc:creator>NicolasP</dc:creator>
      <dc:date>2013-10-07T07:03:38Z</dc:date>
    </item>
  </channel>
</rss>

