<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIOn) problems</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Analog-Audio-PLL-control-Register-CCM-ANALOG-PLL-AUDIOn-problems/m-p/1351089#M181126</link>
    <description>&lt;P&gt;Hi Zoran&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;gt;I am able to write in this area value of 6, which is way below the allowed range.&lt;/P&gt;
&lt;P&gt;&amp;gt;Why it does allow the rate of 6..&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;it is responsibility of programmer to write correct value, from hardware there is no control&lt;/P&gt;
&lt;P&gt;mechanism. PLL output frequency is described in sect.18.5.1.3.4 Audio PLL (PLL4):&lt;/P&gt;
&lt;P&gt;PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)&lt;/P&gt;
&lt;P&gt;&lt;A id="relatedDocsClick_2" href="https://www.nxp.com/webapp/Download?colCode=IMX6DQRM" target="_blank" rel="noopener"&gt;&lt;STRONG&gt;i.MX 6Dual/6Quad Applications Processor Reference Manual&lt;/STRONG&gt;&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
    <pubDate>Wed, 06 Oct 2021 11:20:14 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2021-10-06T11:20:14Z</dc:date>
    <item>
      <title>Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIOn) problems</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Analog-Audio-PLL-control-Register-CCM-ANALOG-PLL-AUDIOn-problems/m-p/1350783#M181082</link>
      <description>&lt;P&gt;I am wondering about the Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIOn) register.&lt;/P&gt;&lt;P&gt;It is defined here:&lt;/P&gt;&lt;P&gt;i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 6, 05/2020&lt;/P&gt;&lt;P&gt;18.7.8 Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIOn)&lt;/P&gt;&lt;P&gt;The problem I have is the following:&lt;/P&gt;&lt;P&gt;The first 7 bits are the integer part of the multiplier, and in the description of this bit array it says:&lt;/P&gt;&lt;P&gt;DIV_SELECT - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.&lt;/P&gt;&lt;P&gt;I am able to write in this area value of 6, which is way below the allowed range.&lt;/P&gt;&lt;P&gt;Why it does allow the rate of 6 (with the fraction it is 6.144), and does the following:&lt;/P&gt;&lt;P&gt;To explain more directly: 6 &amp;lt;&amp;lt; 27!!!&lt;/P&gt;&lt;P&gt;pll4_bypass_src 0 0 24000000 0 0&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; pll4 0 0 147456000 0 0&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; pll4_bypass 0 0 147456000 0 0&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; pll4_audio 0 0 147456000 0 0&lt;/P&gt;&lt;P&gt;Any logical explanation of this significant problem???&lt;/P&gt;&lt;P&gt;zee_z&lt;/P&gt;&lt;P&gt;_______&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 05 Oct 2021 19:29:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Analog-Audio-PLL-control-Register-CCM-ANALOG-PLL-AUDIOn-problems/m-p/1350783#M181082</guid>
      <dc:creator>zee_z</dc:creator>
      <dc:date>2021-10-05T19:29:30Z</dc:date>
    </item>
    <item>
      <title>Re: Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIOn) problems</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Analog-Audio-PLL-control-Register-CCM-ANALOG-PLL-AUDIOn-problems/m-p/1351089#M181126</link>
      <description>&lt;P&gt;Hi Zoran&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;gt;I am able to write in this area value of 6, which is way below the allowed range.&lt;/P&gt;
&lt;P&gt;&amp;gt;Why it does allow the rate of 6..&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;it is responsibility of programmer to write correct value, from hardware there is no control&lt;/P&gt;
&lt;P&gt;mechanism. PLL output frequency is described in sect.18.5.1.3.4 Audio PLL (PLL4):&lt;/P&gt;
&lt;P&gt;PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)&lt;/P&gt;
&lt;P&gt;&lt;A id="relatedDocsClick_2" href="https://www.nxp.com/webapp/Download?colCode=IMX6DQRM" target="_blank" rel="noopener"&gt;&lt;STRONG&gt;i.MX 6Dual/6Quad Applications Processor Reference Manual&lt;/STRONG&gt;&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
      <pubDate>Wed, 06 Oct 2021 11:20:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Analog-Audio-PLL-control-Register-CCM-ANALOG-PLL-AUDIOn-problems/m-p/1351089#M181126</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2021-10-06T11:20:14Z</dc:date>
    </item>
    <item>
      <title>Re: Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIOn) problems</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Analog-Audio-PLL-control-Register-CCM-ANALOG-PLL-AUDIOn-problems/m-p/1351692#M181174</link>
      <description>&lt;P&gt;Privet Igor,&lt;/P&gt;&lt;P&gt;This is not a viable/correct solution, I should say. There are two of them, how to properly handle such a situation.&lt;/P&gt;&lt;P&gt;1. By HW. Your HW design team should put the HW exception handling&amp;nbsp;DIV_SELECT. Anything which is out of range [27..54] should produce an internal exception, either as warning, either as fatal exception. I would go with the first proposal, adding a KERN_WARNING message to dmesg.&lt;/P&gt;&lt;P&gt;2. By SW. The CCM driver should inspect the&amp;nbsp;DIV_SELECT range upon filling it, and if out of range [27..54] to announce the proper KERN_WARNING message to dmesg.&lt;/P&gt;&lt;P&gt;Zee&lt;/P&gt;&lt;P&gt;_______&lt;/P&gt;</description>
      <pubDate>Thu, 07 Oct 2021 07:43:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Analog-Audio-PLL-control-Register-CCM-ANALOG-PLL-AUDIOn-problems/m-p/1351692#M181174</guid>
      <dc:creator>zee_z</dc:creator>
      <dc:date>2021-10-07T07:43:07Z</dc:date>
    </item>
  </channel>
</rss>

