i.MX ProcessorsのトピックRe: I.MX7 power sequencing

I.MX7 power sequencing

NIKHITHAANTONY — Mon, 04 Oct 2021 17:18:59 GMT

In the datasheet of I.MX7 it is given that, VDD_SOC should powerup before NVCC_DRAM and NVCC_DRAM_CKE. So whether it can be done by software. In hardware design, whether we need to take care anything for delaying NVCC_DRAM and NVCC_DRAM_CKE

Re: I.MX7 power sequencing

igorpadykov — Tue, 05 Oct 2021 00:09:19 GMT

Hi NIKHITHA

>whether it can be done by software..

>whether we need to take care anything for delaying NVCC_DRAM and NVCC_DRAM_CKE

no need.

Best regards
igor

Re: I.MX7 power sequencing

NIKHITHAANTONY — Tue, 05 Oct 2021 05:19:09 GMT

Then How VDD_SOC will become high before NVCC_DRAM and NVCC_DRAM_CKE.

Re: I.MX7 power sequencing

igorpadykov — Tue, 05 Oct 2021 06:56:12 GMT

>How VDD_SOC will become high before NVCC_DRAM and NVCC_DRAM_CKE

in hardware. Use appropriate PMIC with power-up sequence compatible with i.MX7D datasheet

requirements.

Best regards
igor

Re: I.MX7 power sequencing

NIKHITHAANTONY — Tue, 05 Oct 2021 09:04:55 GMT

We designed I.MX7 processor as per SABRE board. In that PMIC PF3000 is used.

So there will be correct power sequencing..right?

Re: I.MX7 power sequencing

igorpadykov — Tue, 05 Oct 2021 09:49:31 GMT

>We designed I.MX7 processor as per SABRE board. In that PMIC PF3000 is used.

>So there will be correct power sequencing..right?

right