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    <title>topic Re: imx6dl CPU frequence could not be 996000 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx6dl-CPU-frequence-could-not-be-996000/m-p/1341330#M180205</link>
    <description>&lt;P&gt;Hi&amp;nbsp; 铭恒&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;some parts like industrial work up to 800MHz only, software can read fuse "Temperature Grade",&lt;/P&gt;
&lt;P&gt;Table 1. Example Orderable Part Numbers&amp;nbsp; &lt;A id="relatedDocsClick_1" href="https://www.nxp.com/docs/en/data-sheet/IMX6SDLIEC.pdf" target="_blank" rel="noopener"&gt;&lt;STRONG&gt;i.MX 6Solo/6DualLite Applications Processors for Industrial Products &lt;/STRONG&gt;&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
    <pubDate>Thu, 16 Sep 2021 07:38:08 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2021-09-16T07:38:08Z</dc:date>
    <item>
      <title>imx6dl CPU frequence could not be 996000</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6dl-CPU-frequence-could-not-be-996000/m-p/1341078#M180184</link>
      <description>&lt;P&gt;&lt;STRONG&gt;Hi all&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;I find the CPU frequence could not be 996000, here is the cpu-info:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;cpufreq-info &lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;cpufrequtils 008: cpufreq-info (C) Dominik Brodowski 2004-2009&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Report errors and bugs to cpufreq@vger.kernel.org, please.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;analyzing CPU 0:&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;driver: imx6q-cpufreq&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;CPUs which run at the same hardware frequency: 0 1&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;CPUs which need to have their frequency coordinated by software: 0 1&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;maximum transition latency: 65.0 us.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;hardware limits: 396 MHz - 792 MHz&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;available frequency steps: 396 MHz, 792 MHz&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;available cpufreq governors: interactive, conservative, userspace, powersave, ondemand, performance&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;current policy: frequency should be within 396 MHz and 792 MHz.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;The governor "performance" may decide which speed to use&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;within this range.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;current CPU frequency is 792 MHz (asserted by call to hardware).&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;cpufreq stats: 396 MHz:1.15%, 792 MHz:98.85% (756)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;analyzing CPU 1:&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;driver: imx6q-cpufreq&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;CPUs which run at the same hardware frequency: 0 1&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;CPUs which need to have their frequency coordinated by software: 0 1&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;maximum transition latency: 65.0 us.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;hardware limits: 396 MHz - 792 MHz&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;available frequency steps: 396 MHz, 792 MHz&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;available cpufreq governors: interactive, conservative, userspace, powersave, ondemand, performance&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;current policy: frequency should be within 396 MHz and 792 MHz.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;The governor "performance" may decide which speed to use&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;within this range.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;current CPU frequency is 792 MHz (asserted by call to hardware).&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;cpufreq stats: 396 MHz:1.15%, 792 MHz:98.85% (756)&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;But the device tree has defined the 996Mhz:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;cpus {&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;#address-cells = &amp;lt;1&amp;gt;;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;#size-cells = &amp;lt;0&amp;gt;;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;cpu0: cpu@0 {&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;compatible = "arm,cortex-a9";&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;device_type = "cpu";&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;reg = &amp;lt;0&amp;gt;;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;next-level-cache = &amp;lt;&amp;amp;L2&amp;gt;;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;operating-points = &amp;lt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;/* kHz uV */&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;996000 1250000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;792000 1175000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;396000 1150000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&amp;gt;;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;fsl,soc-operating-points = &amp;lt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;/* ARM kHz SOC-PU uV */&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;996000 1175000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;792000 1175000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;396000 1175000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&amp;gt;;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;clock-latency = &amp;lt;61036&amp;gt;; /* two CLK32 periods */&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;clocks = &amp;lt;&amp;amp;clks IMX6QDL_CLK_ARM&amp;gt;,&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&amp;lt;&amp;amp;clks IMX6QDL_CLK_PLL2_PFD2_396M&amp;gt;,&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&amp;lt;&amp;amp;clks IMX6QDL_CLK_STEP&amp;gt;,&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&amp;lt;&amp;amp;clks IMX6QDL_CLK_PLL1_SW&amp;gt;,&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&amp;lt;&amp;amp;clks IMX6QDL_CLK_PLL1_SYS&amp;gt;,&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&amp;lt;&amp;amp;clks IMX6QDL_CLK_PLL1&amp;gt;,&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&amp;lt;&amp;amp;clks IMX6QDL_PLL1_BYPASS&amp;gt;,&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&amp;lt;&amp;amp;clks IMX6QDL_PLL1_BYPASS_SRC&amp;gt;;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;clock-names = "arm", "pll2_pfd2_396m", "step",&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;"pll1_sw", "pll1_sys", "pll1",&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;"pll1_bypass", "pll1_bypass_src";&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;arm-supply = &amp;lt;&amp;amp;reg_arm&amp;gt;;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;pu-supply = &amp;lt;&amp;amp;reg_pu&amp;gt;;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;soc-supply = &amp;lt;&amp;amp;reg_soc&amp;gt;;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;};&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;cpu@1 {&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;compatible = "arm,cortex-a9";&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;device_type = "cpu";&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;reg = &amp;lt;1&amp;gt;;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;next-level-cache = &amp;lt;&amp;amp;L2&amp;gt;;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;};&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Is there any condition for that, on hardware or kernel configure?&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Best regards&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Mihan&lt;/P&gt;</description>
      <pubDate>Thu, 16 Sep 2021 03:02:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6dl-CPU-frequence-could-not-be-996000/m-p/1341078#M180184</guid>
      <dc:creator>Mihan</dc:creator>
      <dc:date>2021-09-16T03:02:54Z</dc:date>
    </item>
    <item>
      <title>Re: imx6dl CPU frequence could not be 996000</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6dl-CPU-frequence-could-not-be-996000/m-p/1341330#M180205</link>
      <description>&lt;P&gt;Hi&amp;nbsp; 铭恒&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;some parts like industrial work up to 800MHz only, software can read fuse "Temperature Grade",&lt;/P&gt;
&lt;P&gt;Table 1. Example Orderable Part Numbers&amp;nbsp; &lt;A id="relatedDocsClick_1" href="https://www.nxp.com/docs/en/data-sheet/IMX6SDLIEC.pdf" target="_blank" rel="noopener"&gt;&lt;STRONG&gt;i.MX 6Solo/6DualLite Applications Processors for Industrial Products &lt;/STRONG&gt;&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
      <pubDate>Thu, 16 Sep 2021 07:38:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6dl-CPU-frequence-could-not-be-996000/m-p/1341330#M180205</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2021-09-16T07:38:08Z</dc:date>
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