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  <channel>
    <title>topic Re: i.MX8QXP RMII + 4.19.35 NXP Kernel Not Working in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1337135#M179793</link>
    <description>&lt;P&gt;We were able to fix our problem without a kernel patch. Our kernel is a 4.14.181 with some modified and backported drivers, so maybe our problem wasn't the same as the one described in this posting after all.&lt;/P&gt;&lt;P&gt;See this posting for further details:&lt;A href="https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-Ethernet-Phy-issues/m-p/1331161" target="_self"&gt;i.MX8QXP RMII Ethernet Phy issues&lt;/A&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Wed, 08 Sep 2021 19:48:43 GMT</pubDate>
    <dc:creator>rob_mclean</dc:creator>
    <dc:date>2021-09-08T19:48:43Z</dc:date>
    <item>
      <title>i.MX8QXP RMII + 4.19.35 NXP Kernel Not Working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1211112#M167699</link>
      <description>&lt;P&gt;Dear NXP Community,&lt;/P&gt;&lt;P&gt;i.MX8QXP fec is not responding. There is a link-up with KSZ micrel phy. The MDIO bus is working but the Fec is not responding. The TXEN line is always low.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is the&amp;nbsp;4.19.35 kernel FEC driver for rmii for i.MX8QXP working? The ref-clk is there but the FEC is not transmitting no data.&lt;/P&gt;&lt;DIV class="mceNonEditable lia-copypaste-placeholder"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;P&gt;There is a fixup made for fec driver for RGMII in kernel 4.19.35 [fec_fixup.c] does that mean that kernel 4.19.35 only compatible for RGMII.&amp;nbsp;&lt;/P&gt;&lt;P&gt;/*fec_fixup.c*/&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;static int ar8031_phy_fixup(struct phy_device *dev)&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;{&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;u16 val;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;/* Set RGMII IO voltage to 1.8V */&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;phy_write(dev, 0x1d, 0x1f);&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;phy_write(dev, 0x1e, 0x8);&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;/* Disable phy AR8031 SmartEEE function */&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;phy_write(dev, 0xd, 0x3);&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;phy_write(dev, 0xe, 0x805d);&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;phy_write(dev, 0xd, 0x4003);&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;val = phy_read(dev, 0xe);&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;val &amp;amp;= ~(0x1 &amp;lt;&amp;lt; 8);&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;phy_write(dev, 0xe, val);&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;/* Introduce tx clock delay */&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;phy_write(dev, 0x1d, 0x5);&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;phy_write(dev, 0x1e, 0x100);&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;return 0;&lt;/FONT&gt;&lt;BR /&gt;&lt;FONT size="1 2 3 4 5 6 7"&gt;}&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;As rmii IO requires 3.3 V, does that mean a kernel patch is required for RMII or is the fec_main.c is sufficient for RMII in FEC configuration.&lt;/P&gt;&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/37066"&gt;@igorpadykov&lt;/a&gt;&lt;/P&gt;&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/39586"&gt;@joanxie&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanking in advance. Hoping to hear from the community soon.&lt;/P&gt;&lt;P&gt;Kind Regards,&lt;BR /&gt;Hossain&lt;/P&gt;</description>
      <pubDate>Wed, 13 Jan 2021 12:30:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1211112#M167699</guid>
      <dc:creator>mosaddek_hossai</dc:creator>
      <dc:date>2021-01-13T12:30:06Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8QXP RMII + 4.19.35 NXP Kernel Not Working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1211355#M167715</link>
      <description>&lt;P&gt;Hi Hossain&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;for rmii one can use fsl-imx8mm-ddr3l-val.dts :&lt;/P&gt;
&lt;P&gt;&lt;A href="https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr3l-val.dts?h=imx_4.19.35_1.1.0" target="_blank"&gt;https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr3l-val.dts?h=imx_4.19.35_1.1.0&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;gt;As rmii IO requires 3.3 V, does that mean a kernel patch is required for RMII&lt;/P&gt;
&lt;P&gt;&amp;gt;or is the fec_main.c is sufficient for RMII in FEC configuration.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;fec_main.c is sufficient.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
      <pubDate>Wed, 13 Jan 2021 23:05:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1211355#M167715</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2021-01-13T23:05:13Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8QXP RMII + 4.19.35 NXP Kernel Not Working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1211664#M167749</link>
      <description>&lt;P&gt;Hello Igor,&lt;/P&gt;&lt;P&gt;Thanks a lot for your reply.&lt;/P&gt;&lt;P&gt;The device is similar to what you have provided. I have used reference of Mek board TJA1100 device tree.&lt;/P&gt;&lt;P&gt;My device tree is stated below:&lt;/P&gt;&lt;P&gt;/*Pin Mux*/&lt;/P&gt;&lt;P&gt;pinctrl_fec1: fec1grp {&lt;BR /&gt;fsl,pins = &amp;lt;&lt;BR /&gt;SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020&lt;BR /&gt;SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020&lt;BR /&gt;SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061&amp;nbsp;&lt;BR /&gt;SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x00000061&lt;BR /&gt;SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061&lt;BR /&gt;SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061&lt;BR /&gt;SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 /*broad cast*/&lt;BR /&gt;SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 /*full-duplex =0 */&lt;BR /&gt;SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000021 /*phy add-2=1*/&lt;BR /&gt;SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000061&lt;BR /&gt;SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x00000061 /*sig detect*/&lt;BR /&gt;SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000061 /*reset pin*/&lt;BR /&gt;SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x00000061 /*interrupt*/&lt;/P&gt;&lt;P&gt;&amp;gt;;&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;/* Ethernet */&lt;BR /&gt;&amp;amp;fec1 {&lt;BR /&gt;pinctrl-names = "default";&lt;BR /&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_fec1&amp;gt;;&lt;BR /&gt;clocks = &amp;lt;&amp;amp;clk IMX8QXP_ENET0_IPG_CLK&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8QXP_ENET0_AHB_CLK&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8QXP_ENET0_REF_50MHZ_CLK&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8QXP_ENET0_PTP_CLK&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8QXP_ENET0_TX_CLK&amp;gt;;&lt;BR /&gt;phy-mode = "rmii";&lt;BR /&gt;phy-handle = &amp;lt;&amp;amp;ethphy0&amp;gt;;&lt;BR /&gt;fsl,magic-packet;&lt;BR /&gt;/delete-property/ phy-supply;&lt;BR /&gt;local-mac-address = [d2 85 d0 f2 26 47];&lt;BR /&gt;status = "okay";&lt;BR /&gt;&lt;BR /&gt;mdio {&lt;BR /&gt;#address-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;#size-cells = &amp;lt;0&amp;gt;;&lt;/P&gt;&lt;P&gt;ethphy0: ethernet-phy@1 {&lt;BR /&gt;compatible = "ethernet-phy-ieee802.3-c22";&lt;BR /&gt;reg = &amp;lt;1&amp;gt;;&lt;/P&gt;&lt;P&gt;reset-gpios = &amp;lt;&amp;amp;gpio5 1 GPIO_ACTIVE_LOW&amp;gt;;&lt;BR /&gt;reset-assert-us = &amp;lt;10000&amp;gt;;&lt;BR /&gt;reset-deassert-us = &amp;lt;20000&amp;gt;;&lt;BR /&gt;max-speed = &amp;lt;100&amp;gt;;&lt;BR /&gt;};&lt;BR /&gt;};&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If device tree is correct and the fec driver is also correct, why is the TXEN pin not getting high. Why TX and RX in Fec not responding?&lt;/P&gt;&lt;P&gt;From phy it is also receiving data from Host laptop. Rx line is working, but no response from Fec to tcmpdump or ethtool -S eth0 shows zero data in both Tx and Rx.&lt;/P&gt;&lt;P&gt;Hoping to hear from you soon.&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Kind Regards,&lt;/P&gt;&lt;P&gt;Hossain&lt;/P&gt;</description>
      <pubDate>Thu, 14 Jan 2021 09:23:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1211664#M167749</guid>
      <dc:creator>mosaddek_hossai</dc:creator>
      <dc:date>2021-01-14T09:23:36Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8QXP RMII + 4.19.35 NXP Kernel Not Working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1211700#M167755</link>
      <description>&lt;DIV id="bodyDisplay_0" class="lia-message-body lia-component-message-view-widget-body lia-component-body-signature-highlight-escalation lia-component-message-view-widget-body-signature-highlight-escalation"&gt;
&lt;DIV class="lia-message-body-content"&gt;
&lt;P&gt;Hi Hossain&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;sorry I provided wrong dts example, correct is fsl-imx8qxp-enet2-tja1100.dtsi&lt;/P&gt;
&lt;P&gt;&lt;A href="https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/fsl-imx8qxp-enet2-tja1100.dtsi?h=imx_4.19.35_1.1.0" target="_blank"&gt;https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/fsl-imx8qxp-enet2-tja1100.dtsi?h=imx_4.19.35_1.1.0&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;PRE style="padding: 0px; margin: 0px; color: #000000; font-size: 13.3333px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; text-decoration-style: initial; text-decoration-color: initial;" data-find="_1"&gt;&amp;amp;fec2 {
	pinctrl-0 = &amp;lt;&amp;amp;pinctrl_fec2_rmii&amp;gt;;
	clocks = &amp;lt;&amp;amp;clk IMX8QXP_ENET1_IPG_CLK&amp;gt;,
		 &amp;lt;&amp;amp;clk IMX8QXP_ENET1_AHB_CLK&amp;gt;,
		 &amp;lt;&amp;amp;clk IMX8QXP_ENET1_REF_50MHZ_CLK&amp;gt;,
		 &amp;lt;&amp;amp;clk IMX8QXP_ENET1_PTP_CLK&amp;gt;,
		 &amp;lt;&amp;amp;clk IMX8QXP_ENET1_TX_CLK&amp;gt;;
	phy-mode = "rmii";
	phy-handle = &amp;lt;&amp;amp;ethphy2&amp;gt;;
	/delete-property/ phy-supply;

	mdio {
		#address-cells = &amp;lt;1&amp;gt;;
		#size-cells = &amp;lt;0&amp;gt;;

		ethphy2: ethernet-phy@5 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = &amp;lt;5&amp;gt;;
			tja110x,refclk_in;
		};
	};
};

&amp;amp;iomuxc {
	imx8qxp-mek {
		pinctrl_fec2_rmii: fec2rmiigrp {
			fsl,pins = &amp;lt;
				SC_P_ENET0_MDC_CONN_ENET1_MDC			0x06000020
				SC_P_ENET0_MDIO_CONN_ENET1_MDIO			0x06000020
				SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT		0x06000020
				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0            0x06000020
				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1        0x06000020
				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER        0x06000020
				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL          0x06000020
				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0        0x06000020
				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1        0x06000020
				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL         0x06000020
			&amp;gt;;&lt;/PRE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;additionally one can try to test it in uboot, use ENET1 :&lt;/P&gt;
&lt;P&gt;&lt;A href="https://source.codeaurora.org/external/imx/uboot-imx/tree/include/configs/imx8qxp_arm2.h?h=imx_v2019.04_4.19.35_1.1.0" target="_blank"&gt;https://source.codeaurora.org/external/imx/uboot-imx/tree/include/configs/imx8qxp_arm2.h?h=imx_v2019.04_4.19.35_1.1.0&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c?h=imx_v2019.04_4.19.35_1.1.0" target="_blank"&gt;https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c?h=imx_v2019.04_4.19.35_1.1.0&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;</description>
      <pubDate>Thu, 14 Jan 2021 10:12:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1211700#M167755</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2021-01-14T10:12:10Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8QXP RMII + 4.19.35 NXP Kernel Not Working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1219515#M168227</link>
      <description>&lt;P&gt;Dear NXP Community,&lt;/P&gt;&lt;P&gt;Example device Tree for RMII&amp;nbsp;&lt;A href="https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/fsl-imx8qxp-enet2-tja1100.dtsi?h=imx_4.19.35_1.1.0" target="_blank" rel="nofollow noopener noreferrer"&gt;https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/fsl-imx8qxp-...&lt;/A&gt;&amp;nbsp;will not work for 4.19.35 kernel.&amp;nbsp;&lt;/P&gt;&lt;P&gt;For Ethernet for RMII to work in Linux with 50mHz ref clock out, a patch is needed as the clock parent function for&amp;nbsp;SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT is NULL. So the fec driver reads zero. Second and very important point is setting the magic registers for 3.3 V mode.&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */&lt;BR /&gt;SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */&lt;/P&gt;&lt;P&gt;Finally both in U-boot and Linux RMII ethernet is working.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 22 Jan 2021 09:37:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1219515#M168227</guid>
      <dc:creator>mosaddek_hossai</dc:creator>
      <dc:date>2021-01-22T09:37:36Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8QXP RMII + 4.19.35 NXP Kernel Not Working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1329751#M179104</link>
      <description>&lt;P&gt;You mentioned a patch to the kernel is needed for this to work, but you didn't go into detail about it.&lt;/P&gt;&lt;P&gt;Can you share a reference to that kernel patch to fix the SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT clock parent?&lt;/P&gt;</description>
      <pubDate>Wed, 25 Aug 2021 20:08:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1329751#M179104</guid>
      <dc:creator>rob_mclean</dc:creator>
      <dc:date>2021-08-25T20:08:39Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8QXP RMII + 4.19.35 NXP Kernel Not Working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1330504#M179181</link>
      <description>&lt;P&gt;I've been adding some debug statements to my kernel drivers to figure out what that patch might be, and it looks like the "enet_clk_ref" clock in the fec driver is set to 0MHz when the device tree sets it to be "IMX8QXP_ENET0_REF_50MHZ_CLK".&lt;/P&gt;&lt;P&gt;At this point I'm going to see what clock that references, and how I can get that clock to be the "enet_clk_ref".&lt;/P&gt;&lt;P&gt;I assume my finding that the reference clock inside the FEC is 0MHz is what you meant when you said:&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;SPAN&gt;a patch is needed as the clock parent function for&amp;nbsp;SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT is NULL.&lt;/SPAN&gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 26 Aug 2021 16:49:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1330504#M179181</guid>
      <dc:creator>rob_mclean</dc:creator>
      <dc:date>2021-08-26T16:49:12Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8QXP RMII + 4.19.35 NXP Kernel Not Working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1330589#M179185</link>
      <description>&lt;P&gt;After some more digging I think I found the problem you mentioned.&amp;nbsp; In my linux kernel source code tree I have this file:&amp;nbsp; &amp;lt;kernel root directory&amp;gt;/drivers/clk/imx/clk-imx8qxp.c&lt;/P&gt;&lt;P&gt;In that file, I find this line:&lt;/P&gt;&lt;PRE&gt; clks[IMX8QXP_ENET0_REF_50MHZ_CLK] = imx_clk_gate3_scu("enet0_ref_50_clk", NULL, SC_R_ENET_0, SC_C_DISABLE_50, true);&lt;/PRE&gt;&lt;P&gt;I think the patch you mentioned replaces that "NULL" with something that better identifies the parent clock source.&lt;/P&gt;&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/120421"&gt;@mosaddek_hossai&lt;/a&gt;&amp;nbsp;Can you please share a patch (or just some code, or some hints) to help me solve this issue?&lt;/P&gt;</description>
      <pubDate>Thu, 26 Aug 2021 21:24:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1330589#M179185</guid>
      <dc:creator>rob_mclean</dc:creator>
      <dc:date>2021-08-26T21:24:37Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8QXP RMII + 4.19.35 NXP Kernel Not Working</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1337135#M179793</link>
      <description>&lt;P&gt;We were able to fix our problem without a kernel patch. Our kernel is a 4.14.181 with some modified and backported drivers, so maybe our problem wasn't the same as the one described in this posting after all.&lt;/P&gt;&lt;P&gt;See this posting for further details:&lt;A href="https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-Ethernet-Phy-issues/m-p/1331161" target="_self"&gt;i.MX8QXP RMII Ethernet Phy issues&lt;/A&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 08 Sep 2021 19:48:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-RMII-4-19-35-NXP-Kernel-Not-Working/m-p/1337135#M179793</guid>
      <dc:creator>rob_mclean</dc:creator>
      <dc:date>2021-09-08T19:48:43Z</dc:date>
    </item>
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