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    <title>topic Re: System Software Reset vs, Software Signal in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/System-Software-Reset-vs-Software-Signal/m-p/1336381#M179722</link>
    <description>&lt;P&gt;Gustavo,&lt;/P&gt;&lt;P&gt;The way I've coded my system is that, for production firmware, faults call&amp;nbsp;&lt;SPAN&gt;SRC_DoSoftwareResetARMCore0. If the WDOG1 'early warning' interrupt is triggered, the system attempts to do some cleanup, including writing critical data to flash, then reboots using WDOG_TriggerSystemSoftwareReset(). Of course, if things go badly, the watchdog will eventually reboot the system, just not as gracefully as I would like.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Does this sound like a reasonable approach, or should I be using&amp;nbsp;WDOG_TriggerSystemSoftwareReset() for the faults, too?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Jeff&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Wed, 08 Sep 2021 01:45:47 GMT</pubDate>
    <dc:creator>jeffthompson</dc:creator>
    <dc:date>2021-09-08T01:45:47Z</dc:date>
    <item>
      <title>System Software Reset vs, Software Signal</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/System-Software-Reset-vs-Software-Signal/m-p/1331282#M179274</link>
      <description>&lt;P&gt;What are the subtleties between using&amp;nbsp;&lt;SPAN&gt;SRC_DoSoftwareResetARMCore0( SRC )&amp;nbsp;&lt;/SPAN&gt;and&amp;nbsp;&lt;SPAN&gt;WDOG_TriggerSystemSoftwareReset( WDOG1 ) in terms of how they work? The latter seems to work more reliably for our purposes than the former, but I'm not sure why.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Sat, 28 Aug 2021 17:29:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/System-Software-Reset-vs-Software-Signal/m-p/1331282#M179274</guid>
      <dc:creator>jeffthompson</dc:creator>
      <dc:date>2021-08-28T17:29:04Z</dc:date>
    </item>
    <item>
      <title>Re: System Software Reset vs, Software Signal</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/System-Software-Reset-vs-Software-Signal/m-p/1336335#M179713</link>
      <description>&lt;P&gt;Hello Jeffthompson,&lt;/P&gt;
&lt;P&gt;Both would be cold resets, albeit originated in different ways.&lt;/P&gt;
&lt;P&gt;SRC_DoSoftwareResetARMCore0 would do a software reset of the ARM Core0 only, by asserting the SRC_SCR[core0_rst], which is a self-clearing bit.&lt;/P&gt;
&lt;P&gt;WDOG_TriggerSystemSoftwareReset asserts WCR[WDA] which asserts WDOG_B, so it’s functionally identical to the WDOG time-out triggering the WDOG_B signal.&lt;/P&gt;
&lt;P&gt;I hope that this information helps.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Gustavo&lt;/P&gt;</description>
      <pubDate>Wed, 08 Sep 2021 00:09:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/System-Software-Reset-vs-Software-Signal/m-p/1336335#M179713</guid>
      <dc:creator>gusarambula</dc:creator>
      <dc:date>2021-09-08T00:09:36Z</dc:date>
    </item>
    <item>
      <title>Re: System Software Reset vs, Software Signal</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/System-Software-Reset-vs-Software-Signal/m-p/1336381#M179722</link>
      <description>&lt;P&gt;Gustavo,&lt;/P&gt;&lt;P&gt;The way I've coded my system is that, for production firmware, faults call&amp;nbsp;&lt;SPAN&gt;SRC_DoSoftwareResetARMCore0. If the WDOG1 'early warning' interrupt is triggered, the system attempts to do some cleanup, including writing critical data to flash, then reboots using WDOG_TriggerSystemSoftwareReset(). Of course, if things go badly, the watchdog will eventually reboot the system, just not as gracefully as I would like.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Does this sound like a reasonable approach, or should I be using&amp;nbsp;WDOG_TriggerSystemSoftwareReset() for the faults, too?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Jeff&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 08 Sep 2021 01:45:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/System-Software-Reset-vs-Software-Signal/m-p/1336381#M179722</guid>
      <dc:creator>jeffthompson</dc:creator>
      <dc:date>2021-09-08T01:45:47Z</dc:date>
    </item>
    <item>
      <title>Re: System Software Reset vs, Software Signal</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/System-Software-Reset-vs-Software-Signal/m-p/1338482#M179922</link>
      <description>&lt;P&gt;Hello Jeffthompson,&lt;/P&gt;
&lt;P&gt;Would you please confirm which i.MXRT processor you are using? If it’s one that has a second core that you may want to keep running then it would make sense to reset only the core0 in theory, otherwise I would probably opt for the WDOG reset for the faults too.&lt;/P&gt;
&lt;P&gt;Knowing which i.MXRT you are using may also allow me to investigate if we have more information on how resetting the core0 differs from the WDOG reset on that MCU in particular.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Gustavo&lt;/P&gt;</description>
      <pubDate>Fri, 10 Sep 2021 14:28:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/System-Software-Reset-vs-Software-Signal/m-p/1338482#M179922</guid>
      <dc:creator>gusarambula</dc:creator>
      <dc:date>2021-09-10T14:28:43Z</dc:date>
    </item>
    <item>
      <title>Re: System Software Reset vs, Software Signal</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/System-Software-Reset-vs-Software-Signal/m-p/1338499#M179924</link>
      <description>&lt;P&gt;Thanks, Gustavo. I'm using the MIMXRT1026DVJ6A, so I'll change my code to use the WDOG reset instead of the SRC reset.&lt;/P&gt;</description>
      <pubDate>Fri, 10 Sep 2021 15:21:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/System-Software-Reset-vs-Software-Signal/m-p/1338499#M179924</guid>
      <dc:creator>jeffthompson</dc:creator>
      <dc:date>2021-09-10T15:21:23Z</dc:date>
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