topic DQ mapping issue in i.MX Processors

DQ mapping issue

simonng — Tue, 24 Aug 2021 02:22:32 GMT

Hi NXP Team,

We are using i.MX8MQ processor with scrambled channel and data mapping to the LPDDR4 memory on our board. We are writing some test programs on the uboot to test the LPDDR4 memory. When I define a data and write it to the memory, what is the final data write to the DRAM?

For example,

unsigned long testdata = 0xFEDCBA9876543210;

with the above channel and data configuration, what data will be written to the DRAM?

Thanks.

Re: DQ mapping issue

Yuri — Wed, 25 Aug 2021 04:40:06 GMT

@simonng
Hello,

Low byte 0x10 will be mapped to memory chan B 0x04: 4-th bit of i.MX8 to 2 bit of the memory
.... and so on.

Regards,
Yuri.

Re: DQ mapping issue

simonng — Wed, 25 Aug 2021 05:03:32 GMT

Hi Yuri,

Thanks for your reply.

Regards,

Simon