i.MX ProcessorsのトピックRe: iMX6UL DDR3 layout question https://community.nxp.com/t5/i-MX-Processors/iMX6UL-DDR3-layout-question/m-p/1323536#M178464 <P>and these is my DDR3 trace length, is this ok?</P><TABLE width="200"><TBODY><TR><TD width="128">DRAM_CLK0_N</TD><TD width="72">677.746</TD></TR><TR><TD>DRAM_CLK0_P</TD><TD>676.912</TD></TR><TR><TD>&nbsp;</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR0</TD><TD>677.742</TD></TR><TR><TD>DRAM_ADDR1</TD><TD>676.138</TD></TR><TR><TD>DRAM_ADDR2</TD><TD>677.506</TD></TR><TR><TD>DRAM_ADDR3</TD><TD>677.819</TD></TR><TR><TD>DRAM_ADDR4</TD><TD>677.513</TD></TR><TR><TD>DRAM_ADDR5</TD><TD>678.519</TD></TR><TR><TD>DRAM_ADDR6</TD><TD>674.767</TD></TR><TR><TD>DRAM_ADDR7</TD><TD>678.011</TD></TR><TR><TD>DRAM_ADDR8</TD><TD>677.046</TD></TR><TR><TD>DRAM_ADDR9</TD><TD>678.917</TD></TR><TR><TD>DRAM_ADDR10</TD><TD>677.574</TD></TR><TR><TD>DRAM_ADDR11</TD><TD>677.451</TD></TR><TR><TD>DRAM_ADDR12</TD><TD>676.535</TD></TR><TR><TD>DRAM_ADDR13</TD><TD>677.266</TD></TR><TR><TD>DRAM_ADDR14</TD><TD>675.765</TD></TR><TR><TD>DRAM_ADDR15</TD><TD>677.765</TD></TR><TR><TD>DRAM_BA0</TD><TD>677.501</TD></TR><TR><TD>DRAM_BA1</TD><TD>678.4</TD></TR><TR><TD>DRAM_BA2</TD><TD>677.658</TD></TR><TR><TD>DRAM_CAS</TD><TD>676.385</TD></TR><TR><TD>DRAM_CKE0</TD><TD>677.785</TD></TR><TR><TD>DRAM_CKE1</TD><TD>677.996</TD></TR><TR><TD>DRAM_CS0</TD><TD>677.669</TD></TR><TR><TD>DRAM_CS1</TD><TD>677.023</TD></TR><TR><TD>DRAM_ODT0</TD><TD>678.446</TD></TR><TR><TD>DRAM_ODT1</TD><TD>677.933</TD></TR><TR><TD>DRAM_RAS</TD><TD>677.71</TD></TR><TR><TD>DRAM_RESET</TD><TD>639.338</TD></TR><TR><TD>DRAM_WE</TD><TD>677.802</TD></TR><TR><TD>&nbsp;</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DQS0_N</TD><TD>976.508</TD></TR><TR><TD>DRAM_DQS0_P</TD><TD>974.327</TD></TR><TR><TD>DRAM_DQM0</TD><TD>940.449</TD></TR><TR><TD>DRAM_DATA0</TD><TD>940.361</TD></TR><TR><TD>DRAM_DATA1</TD><TD>940.012</TD></TR><TR><TD>DRAM_DATA2</TD><TD>940.732</TD></TR><TR><TD>DRAM_DATA3</TD><TD>940.265</TD></TR><TR><TD>DRAM_DATA4</TD><TD>940.431</TD></TR><TR><TD>DRAM_DATA5</TD><TD>940.171</TD></TR><TR><TD>DRAM_DATA6</TD><TD>940.517</TD></TR><TR><TD>DRAM_DATA7</TD><TD>940.253</TD></TR><TR><TD>&nbsp;</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DQS1_N</TD><TD>775.96</TD></TR><TR><TD>DRAM_DQS1_P</TD><TD>774.569</TD></TR><TR><TD>DRAM_DQM1</TD><TD>775.283</TD></TR><TR><TD>DRAM_DATA8</TD><TD>775.646</TD></TR><TR><TD>DRAM_DATA9</TD><TD>775.115</TD></TR><TR><TD>DRAM_DATA10</TD><TD>775.827</TD></TR><TR><TD>DRAM_DATA11</TD><TD>775.737</TD></TR><TR><TD>DRAM_DATA12</TD><TD>775.733</TD></TR><TR><TD>DRAM_DATA13</TD><TD>775.446</TD></TR><TR><TD>DRAM_DATA14</TD><TD>775.21</TD></TR><TR><TD>DRAM_DATA15</TD><TD>775.003</TD></TR></TBODY></TABLE> Mon, 16 Aug 2021 00:51:29 GMT mengxp 2021-08-16T00:51:29Z iMX6UL DDR3 layout question https://community.nxp.com/t5/i-MX-Processors/iMX6UL-DDR3-layout-question/m-p/1323535#M178463 <P>Hi all,</P><P>the DDR3 layout detail in iMX6UL design guide is not clear for me</P><P>so I read the IMX6UL 14x14 EVK board file&nbsp;LAY-28617_C2.brd</P><P>following table is the DDR3 trace length I extract from Altium</P><TABLE width="316"><TBODY><TR><TD width="172">DRAM_SDCLK0_N</TD><TD width="72">1474.547</TD><TD width="72">&nbsp;</TD></TR><TR><TD>DRAM_SDCLK0_P</TD><TD>1478.036</TD><TD>&nbsp;</TD></TR><TR><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR0</TD><TD>1456.372</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR1</TD><TD>1383.264</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR2</TD><TD>1383.865</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR3</TD><TD>1377.21</TD><TD>minimum</TD></TR><TR><TD>DRAM_ADDR4</TD><TD>1460.093</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR5</TD><TD>1385.589</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR6</TD><TD>1385.052</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR7</TD><TD>1468.929</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR8</TD><TD>1456.697</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR9</TD><TD>1389.506</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR10</TD><TD>1463.336</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR11</TD><TD>1455.482</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR12</TD><TD>1457.502</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR13</TD><TD>1489.418</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR14</TD><TD>1381.572</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR15</TD><TD>1455.742</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_SDBA0</TD><TD>1391.499</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_SDBA1</TD><TD>1378.845</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_SDBA2</TD><TD>1392.906</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_RAS_B</TD><TD>1456.112</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_CAS_B</TD><TD>1396.785</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_SDWE_B</TD><TD>1379.31</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_CS0_B</TD><TD>1397.098</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_CS1_B</TD><TD>1457.976</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_SDCKE0</TD><TD>1500.327</TD><TD>maximum</TD></TR><TR><TD>DRAM_SDCKE1</TD><TD>1475.134</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ODT0</TD><TD>1388.913</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ODT1</TD><TD>1456.594</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_RESET_B</TD><TD>1394.69</TD><TD>&nbsp;</TD></TR><TR><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_SDQS0_N</TD><TD>1111.194</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_SDQS0_P</TD><TD>1110.196</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DQM0</TD><TD>992.587</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA0</TD><TD>991.092</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA1</TD><TD>997.784</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA2</TD><TD>998.88</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA3</TD><TD>992.781</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA4</TD><TD>998.4</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA5</TD><TD>998.351</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA6</TD><TD>995.83</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA7</TD><TD>997.645</TD><TD>&nbsp;</TD></TR><TR><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_SDQS1_N</TD><TD>1024.715</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_SDQS1_P</TD><TD>1023.824</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DQM1</TD><TD>1019.876</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA8</TD><TD>1021.889</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA9</TD><TD>1020.667</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA10</TD><TD>1025.673</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA11</TD><TD>1029.274</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA12</TD><TD>1027.033</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA13</TD><TD>1025.052</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA14</TD><TD>1025.595</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DATA15</TD><TD>1022.981</TD><TD>&nbsp;</TD></TR></TBODY></TABLE><P>&nbsp;</P><P>most of the signals trace length is reasonable</P><P>but the SDQS0_P/SDQS0_N is a question ,why they are traced about ~1110 mil?</P><P>should they trace to ~1000 mil around?</P><P>and following picture is&nbsp;SDQS0_P/SDQS0_N trace, they can be traced to ~1000,</P><P>why 1110 mil?</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="sdqs0.png" style="width: 956px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/152879iBEFFC83003C15E78/image-size/large?v=v2&amp;px=999" role="button" title="sdqs0.png" alt="sdqs0.png" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">sdqs0.png</span></span></P> Mon, 16 Aug 2021 00:45:02 GMT https://community.nxp.com/t5/i-MX-Processors/iMX6UL-DDR3-layout-question/m-p/1323535#M178463 mengxp 2021-08-16T00:45:02Z Re: iMX6UL DDR3 layout question https://community.nxp.com/t5/i-MX-Processors/iMX6UL-DDR3-layout-question/m-p/1323536#M178464 <P>and these is my DDR3 trace length, is this ok?</P><TABLE width="200"><TBODY><TR><TD width="128">DRAM_CLK0_N</TD><TD width="72">677.746</TD></TR><TR><TD>DRAM_CLK0_P</TD><TD>676.912</TD></TR><TR><TD>&nbsp;</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_ADDR0</TD><TD>677.742</TD></TR><TR><TD>DRAM_ADDR1</TD><TD>676.138</TD></TR><TR><TD>DRAM_ADDR2</TD><TD>677.506</TD></TR><TR><TD>DRAM_ADDR3</TD><TD>677.819</TD></TR><TR><TD>DRAM_ADDR4</TD><TD>677.513</TD></TR><TR><TD>DRAM_ADDR5</TD><TD>678.519</TD></TR><TR><TD>DRAM_ADDR6</TD><TD>674.767</TD></TR><TR><TD>DRAM_ADDR7</TD><TD>678.011</TD></TR><TR><TD>DRAM_ADDR8</TD><TD>677.046</TD></TR><TR><TD>DRAM_ADDR9</TD><TD>678.917</TD></TR><TR><TD>DRAM_ADDR10</TD><TD>677.574</TD></TR><TR><TD>DRAM_ADDR11</TD><TD>677.451</TD></TR><TR><TD>DRAM_ADDR12</TD><TD>676.535</TD></TR><TR><TD>DRAM_ADDR13</TD><TD>677.266</TD></TR><TR><TD>DRAM_ADDR14</TD><TD>675.765</TD></TR><TR><TD>DRAM_ADDR15</TD><TD>677.765</TD></TR><TR><TD>DRAM_BA0</TD><TD>677.501</TD></TR><TR><TD>DRAM_BA1</TD><TD>678.4</TD></TR><TR><TD>DRAM_BA2</TD><TD>677.658</TD></TR><TR><TD>DRAM_CAS</TD><TD>676.385</TD></TR><TR><TD>DRAM_CKE0</TD><TD>677.785</TD></TR><TR><TD>DRAM_CKE1</TD><TD>677.996</TD></TR><TR><TD>DRAM_CS0</TD><TD>677.669</TD></TR><TR><TD>DRAM_CS1</TD><TD>677.023</TD></TR><TR><TD>DRAM_ODT0</TD><TD>678.446</TD></TR><TR><TD>DRAM_ODT1</TD><TD>677.933</TD></TR><TR><TD>DRAM_RAS</TD><TD>677.71</TD></TR><TR><TD>DRAM_RESET</TD><TD>639.338</TD></TR><TR><TD>DRAM_WE</TD><TD>677.802</TD></TR><TR><TD>&nbsp;</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DQS0_N</TD><TD>976.508</TD></TR><TR><TD>DRAM_DQS0_P</TD><TD>974.327</TD></TR><TR><TD>DRAM_DQM0</TD><TD>940.449</TD></TR><TR><TD>DRAM_DATA0</TD><TD>940.361</TD></TR><TR><TD>DRAM_DATA1</TD><TD>940.012</TD></TR><TR><TD>DRAM_DATA2</TD><TD>940.732</TD></TR><TR><TD>DRAM_DATA3</TD><TD>940.265</TD></TR><TR><TD>DRAM_DATA4</TD><TD>940.431</TD></TR><TR><TD>DRAM_DATA5</TD><TD>940.171</TD></TR><TR><TD>DRAM_DATA6</TD><TD>940.517</TD></TR><TR><TD>DRAM_DATA7</TD><TD>940.253</TD></TR><TR><TD>&nbsp;</TD><TD>&nbsp;</TD></TR><TR><TD>DRAM_DQS1_N</TD><TD>775.96</TD></TR><TR><TD>DRAM_DQS1_P</TD><TD>774.569</TD></TR><TR><TD>DRAM_DQM1</TD><TD>775.283</TD></TR><TR><TD>DRAM_DATA8</TD><TD>775.646</TD></TR><TR><TD>DRAM_DATA9</TD><TD>775.115</TD></TR><TR><TD>DRAM_DATA10</TD><TD>775.827</TD></TR><TR><TD>DRAM_DATA11</TD><TD>775.737</TD></TR><TR><TD>DRAM_DATA12</TD><TD>775.733</TD></TR><TR><TD>DRAM_DATA13</TD><TD>775.446</TD></TR><TR><TD>DRAM_DATA14</TD><TD>775.21</TD></TR><TR><TD>DRAM_DATA15</TD><TD>775.003</TD></TR></TBODY></TABLE> Mon, 16 Aug 2021 00:51:29 GMT https://community.nxp.com/t5/i-MX-Processors/iMX6UL-DDR3-layout-question/m-p/1323536#M178464 mengxp 2021-08-16T00:51:29Z Re: iMX6UL DDR3 layout question https://community.nxp.com/t5/i-MX-Processors/iMX6UL-DDR3-layout-question/m-p/1323787#M178493 <P><a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/106124">@mengxp</a><BR />Hello<STRONG>,<BR /><BR /></STRONG>&nbsp; according to Table 22 (DDR3 routing by byte group) of Hardware Development Guide<BR />signals in byte group should match the signals of each byte group ± 25 mils.<BR />Match the differential signals of DQS ± 10 mils</P> <P><A href="https://www.nxp.com/webapp/Download?colCode=IMX6ULHDG" target="_blank">https://www.nxp.com/webapp/Download?colCode=IMX6ULHDG</A></P> <P>&nbsp; Looks like no problem in Your case.</P> <P>Regards,<BR />Yuri.</P> <P>&nbsp;</P> Mon, 16 Aug 2021 07:59:23 GMT https://community.nxp.com/t5/i-MX-Processors/iMX6UL-DDR3-layout-question/m-p/1323787#M178493 Yuri 2021-08-16T07:59:23Z