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    <title>topic Re: i.MX8M Mini Minimum Power Up Requirements in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-Minimum-Power-Up-Requirements/m-p/1311359#M177291</link>
    <description>&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;Thank you for the link to the HDG, I will read it to find any specification requirements that are missing from the datasheet.&lt;/P&gt;</description>
    <pubDate>Wed, 21 Jul 2021 14:57:38 GMT</pubDate>
    <dc:creator>kevinl</dc:creator>
    <dc:date>2021-07-21T14:57:38Z</dc:date>
    <item>
      <title>i.MX8M Mini Minimum Power Up Requirements</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-Minimum-Power-Up-Requirements/m-p/1308646#M177018</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I was looking at Figure 3 in i.MX8M Mini datasheet (&lt;A href="https://www.nxp.com/docs/en/data-sheet/IMX8MMCEC.pdf" target="_blank"&gt;https://www.nxp.com/docs/en/data-sheet/IMX8MMCEC.pdf&lt;/A&gt;) with Table 17 and it looks like the minimum time from start of one rail to start of the next is 0 ms for all rails, including POR_B deassert, which seems strange to me.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is it true you can just enable everything, including POR_B at the same time, ignoring the ramp time of the regulators? Or are there hidden requirements other than the:&lt;/P&gt;&lt;P&gt;"For ramp up requirement, only VDD_ANA0_1P8 has 5 s minimum requirement, others do not have such requirement. During power-up, make sure NVCC_xxx - PVCCx_1P8 &amp;lt; 2 V."&lt;/P&gt;&lt;P&gt;For example:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Power_Up_Spec_Allowed.JPG" style="width: 701px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/149974iA09833337A3EC7F8/image-size/large?v=v2&amp;amp;px=999" role="button" title="Power_Up_Spec_Allowed.JPG" alt="Power_Up_Spec_Allowed.JPG" /&gt;&lt;/span&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 15 Jul 2021 21:18:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-Minimum-Power-Up-Requirements/m-p/1308646#M177018</guid>
      <dc:creator>kevinl</dc:creator>
      <dc:date>2021-07-15T21:18:06Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8M Mini Minimum Power Up Requirements</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-Minimum-Power-Up-Requirements/m-p/1308865#M177046</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/67780"&gt;@kevinl&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp; In the datasheet, we have the VDD_SOC, VDD_ANA_0P8, VDD_ARM_PLL_0P8, etc., &lt;BR /&gt;referenced to PMIC_ON_REQ signal. Therefore the rising of the mentioned supply voltages &lt;BR /&gt;(VDD_SOC, VDD_ANA_0P8, VDD_ARM_PLL_0P8, etc) should be performed (possibly &lt;BR /&gt;simultaneously) after VDD_SNVS_0P8 and NVCC_SNVS_1P8 are stable.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Fri, 16 Jul 2021 06:55:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-Minimum-Power-Up-Requirements/m-p/1308865#M177046</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2021-07-16T06:55:42Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8M Mini Minimum Power Up Requirements</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-Minimum-Power-Up-Requirements/m-p/1310645#M177223</link>
      <description>&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;Thank you for the quick response!&lt;/P&gt;&lt;P&gt;To confirm, POR_B de-assert is not gated by any rail except PMIC_ON_REQ and RTC_RESET_B? As in, it can go high before VDD_SOC completes it's ramp for example?&lt;/P&gt;</description>
      <pubDate>Tue, 20 Jul 2021 17:22:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-Minimum-Power-Up-Requirements/m-p/1310645#M177223</guid>
      <dc:creator>kevinl</dc:creator>
      <dc:date>2021-07-20T17:22:44Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8M Mini Minimum Power Up Requirements</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-Minimum-Power-Up-Requirements/m-p/1311119#M177265</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/67780"&gt;@kevinl&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp; According to Table 8 (Reset and ON/OFF recommendations) of&lt;BR /&gt;i.MX 8M Mini Hardware Developer’s Guide, User's Guide, Rev. 2, 11/2020:&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; The POR_B input must be asserted at powered up and remain asserted &lt;BR /&gt;until the last power rail for devices required for system boot are at their &lt;BR /&gt;working voltage.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/Download?colCode=IMX8MMHDG" target="_blank"&gt;https://www.nxp.com/webapp/Download?colCode=IMX8MMHDG&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Wed, 21 Jul 2021 08:32:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-Minimum-Power-Up-Requirements/m-p/1311119#M177265</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2021-07-21T08:32:01Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8M Mini Minimum Power Up Requirements</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-Minimum-Power-Up-Requirements/m-p/1311359#M177291</link>
      <description>&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;Thank you for the link to the HDG, I will read it to find any specification requirements that are missing from the datasheet.&lt;/P&gt;</description>
      <pubDate>Wed, 21 Jul 2021 14:57:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-Minimum-Power-Up-Requirements/m-p/1311359#M177291</guid>
      <dc:creator>kevinl</dc:creator>
      <dc:date>2021-07-21T14:57:38Z</dc:date>
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