i.MX6 eCSPI Write/Read Timing Understanding

chris_lambrecht — Mon, 19 Jul 2021 04:46:31 GMT

In looking at the Electrical Characteristics for the i.MX6 ULL processor (IMX6ULLCED PDF), Figure 35 and Table 47 indicate that there is a SPI Write timing of 15ns while there is a SPI Read Timing of 43ns (CS1) in Master Mode.

I read this to mean that the MISO data will not be registered correctly by the i.MX6 ULL processor if the i.MX6 is generating a SPI SCLK at a frequency greater than 23MHz (43ns). Therefore, if the i.MX6 wants to be able to register MISO data correctly, it must always run with a SPI clock slower than 43ns, or change between a faster clock when it doesn't care about the MISO data and a slower clock, when it does care to receive valid data.

Is this a correct understanding of these two timing parameters?

Thanks,

Chris

Re: i.MX6 eCSPI Write/Read Timing Understanding

igorpadykov — Mon, 19 Jul 2021 05:48:20 GMT

Hi Chris

yes your understanding is correct.

Best regards
igor

Re: i.MX6 eCSPI Write/Read Timing Understanding

chris_lambrecht — Tue, 20 Jul 2021 04:17:30 GMT

Thanks!!

topic Re: i.MX6 eCSPI Write/Read Timing Understanding in i.MX Processors

i.MX6 eCSPI Write/Read Timing Understanding

Re: i.MX6 eCSPI Write/Read Timing Understanding

Re: i.MX6 eCSPI Write/Read Timing Understanding