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    <title>topic Re: IMX8QXP MIPI CSI voltage level in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-MIPI-CSI-voltage-level/m-p/1303432#M176480</link>
    <description>&lt;P&gt;&amp;gt;What MIPI specs or standards can its MIPI CSI interfaces be connected with?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;MIPI CSI2 Specification V1.3, MIPI D-PHY specification V1.2)&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;gt;You had mentioned the IO supplies of the 2 MIPI power rails are meant for GPIO signals.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;sorry I did not answer that.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;gt;Can I say that when mux pin use as MIPI CSI2, those differential MIPI data and clock signals would match &amp;gt;the external D-PHY operating at 1.2V?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;they match values defined in MIPI CSI2 Specification V1.3, MIPI D-PHY specification V1.2)&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
    <pubDate>Wed, 07 Jul 2021 00:15:42 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2021-07-07T00:15:42Z</dc:date>
    <item>
      <title>IMX8QXP MIPI CSI voltage level</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-MIPI-CSI-voltage-level/m-p/1302740#M176436</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;I would like to connect the MIPI-CSI 4-lanes interfaces of iMX8 QXP to a CSI-2 bridge (i.e. lattice LIF-MD6000) to receive parallel raw pixels data from sensor. However, I am quite confuse as the IO supplies for its MIPI PHY and GPIO are 1V on VDD_MIPI_1P0 pins and 1.8V on VDD_MIPI_1P8 pins. Based on MIPI CSI-2 standards, 1.2V is the typical/common D-PHY voltage supply to work with.&lt;/P&gt;&lt;P&gt;Would the intended electrical connections be an issue? What can be the workaround solution?&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;Rdgs,&lt;BR /&gt;YK&lt;/P&gt;</description>
      <pubDate>Tue, 06 Jul 2021 04:26:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-MIPI-CSI-voltage-level/m-p/1302740#M176436</guid>
      <dc:creator>YK7</dc:creator>
      <dc:date>2021-07-06T04:26:32Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8QXP MIPI CSI voltage level</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-MIPI-CSI-voltage-level/m-p/1302923#M176443</link>
      <description>&lt;P&gt;Hi YK&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;if bridge complies with&amp;nbsp;MIPI CSI2 Specification V1.3,&amp;nbsp;MIPI D-PHY specification V1.2&lt;/P&gt;
&lt;P&gt;it can be connected with i.MX8M Mini.&lt;/P&gt;
&lt;P&gt;Regarding : " IO supplies for its MIPI PHY and GPIO are 1V on VDD_MIPI_1P0 pins and 1.8V on VDD_MIPI_1P8 pins" - this rule is applicable to GPIO signals, their levels are defined by pad&lt;/P&gt;
&lt;P&gt;power supply value.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
      <pubDate>Tue, 06 Jul 2021 07:17:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-MIPI-CSI-voltage-level/m-p/1302923#M176443</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2021-07-06T07:17:50Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8QXP MIPI CSI voltage level</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-MIPI-CSI-voltage-level/m-p/1302977#M176452</link>
      <description>&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;I am using I.MX8 QXP.&lt;/P&gt;&lt;P&gt;What MIPI specs or standards can its MIPI CSI interfaces be connected with?&lt;/P&gt;&lt;P&gt;You had mentioned the IO supplies of the 2 MIPI power rails are meant for GPIO signals. Can I say that when mux pin use as MIPI CSI2, those differential MIPI data and clock signals would match the external D-PHY operating at 1.2V?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Rdgs, YK&lt;/P&gt;</description>
      <pubDate>Tue, 06 Jul 2021 08:09:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-MIPI-CSI-voltage-level/m-p/1302977#M176452</guid>
      <dc:creator>YK7</dc:creator>
      <dc:date>2021-07-06T08:09:12Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8QXP MIPI CSI voltage level</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-MIPI-CSI-voltage-level/m-p/1303432#M176480</link>
      <description>&lt;P&gt;&amp;gt;What MIPI specs or standards can its MIPI CSI interfaces be connected with?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;MIPI CSI2 Specification V1.3, MIPI D-PHY specification V1.2)&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;gt;You had mentioned the IO supplies of the 2 MIPI power rails are meant for GPIO signals.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;sorry I did not answer that.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;gt;Can I say that when mux pin use as MIPI CSI2, those differential MIPI data and clock signals would match &amp;gt;the external D-PHY operating at 1.2V?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;they match values defined in MIPI CSI2 Specification V1.3, MIPI D-PHY specification V1.2)&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
      <pubDate>Wed, 07 Jul 2021 00:15:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8QXP-MIPI-CSI-voltage-level/m-p/1303432#M176480</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2021-07-07T00:15:42Z</dc:date>
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