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    <title>topic Re: RT1170 EVK FLexRAM allocation in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1302612#M176428</link>
    <description>&lt;P&gt;Hello John,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I'm working on making the proper changes in my community document. Are you still facing the same behavior? If you make these changes in a non-multi-core project, do you face the same behavior?&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Victor&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 05 Jul 2021 23:57:01 GMT</pubDate>
    <dc:creator>victorjimenez</dc:creator>
    <dc:date>2021-07-05T23:57:01Z</dc:date>
    <item>
      <title>RT1170 EVK FLexRAM allocation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1295235#M175767</link>
      <description>&lt;P&gt;Good day all.&lt;/P&gt;&lt;P&gt;It is my first time configuring FlexRAM. I am trying to change the FlexRAM memory allocation on the RT1170EVK board. I have followed the steps from the NXP post&amp;nbsp;&lt;A href="https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Reallocating-the-FlexRAM/ta-p/1117649" target="_blank" rel="noopener"&gt;Reallocating the FlexRAM - NXP Community&lt;/A&gt;&amp;nbsp;and the application note&amp;nbsp;"Using the i.MX RT FlexRAM Rev 3". I would like to only use SRAM_DTC, i.e. 512kB DTCM and 0kB ITCM and 0kB OCRAM.&lt;/P&gt;&lt;P&gt;I have modified the following registers at their corresponding addresses (obtained from the i.MX RT1170 Processor Reference Manual Rev 1):&lt;/P&gt;&lt;P&gt;IOMUXC_GPR_GPR16 - 0x400E4040&lt;/P&gt;&lt;P&gt;IOMUXC_GPR_GPR16 - 0x400E4044&lt;/P&gt;&lt;P&gt;IOMUXC_GPR_GPR16 - 0x400E4048&lt;/P&gt;&lt;P&gt;I edited the ResetISR(void) function in 'startup_mimxrt1176_cm7.c" to be:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dloub_0-1624258916845.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/147552i6700D228200B1448/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dloub_0-1624258916845.png" alt="dloub_0-1624258916845.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;I replaced 'IMAGE_ENTRY_ADDRESS' in 'fsl_flexspi_nor_boot.c' with '(uint32_t)ResetISR' as per the instructions:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dloub_1-1624259041774.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/147553i8928CBC3D529455B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dloub_1-1624259041774.png" alt="dloub_1-1624259041774.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;This resulted in a mupltiple definitions error, therefore I had to comment out 'extern uint32_t ResetISR[];' in 'fsl_flexspi_nor_boot.h':&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dloub_6-1624259816175.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/147559i94D952A73CEBBD1C/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dloub_6-1624259816175.png" alt="dloub_6-1624259816175.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;I changed the linkerscript to correspond to the new DTC size:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dloub_2-1624259101885.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/147554iFCDF44E50F45A1AA/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dloub_2-1624259101885.png" alt="dloub_2-1624259101885.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;And in board.c I modified the MPU (BOARD_ConfigMPU) to match the new memory sizes (based on the assumption that region 4 is the ITC and region 5 is the DTC):&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dloub_3-1624259210934.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/147555iB7FFEDC70B50B64A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dloub_3-1624259210934.png" alt="dloub_3-1624259210934.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;With this configuration and modifications my project compiles fine:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dloub_4-1624259285519.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/147556i717B826B3F4AEBAE/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dloub_4-1624259285519.png" alt="dloub_4-1624259285519.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;But when debugging, my program just stalls and never offers the 'play' option:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dloub_5-1624259459384.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/147558i6D4F0428A4986ADE/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dloub_5-1624259459384.png" alt="dloub_5-1624259459384.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;What am I doing wrong?&lt;/P&gt;</description>
      <pubDate>Mon, 21 Jun 2021 08:44:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1295235#M175767</guid>
      <dc:creator>dloub</dc:creator>
      <dc:date>2021-06-21T08:44:13Z</dc:date>
    </item>
    <item>
      <title>Re: RT1170 EVK FLexRAM allocation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1296609#M175903</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/186535"&gt;@dloub&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; &amp;nbsp;Please check this application note at first:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/docs/en/application-note/AN12077.pdf" target="_blank"&gt;https://www.nxp.com/docs/en/application-note/AN12077.pdf&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;The minimum configuration of OCRAM is 64 KB (see Table 1). This is&amp;nbsp;required due to ROM code requires at least 64 KB of RAM for its&lt;BR /&gt;execution. The minimum OCRAM requirements can be device dependent.&lt;/P&gt;
&lt;P&gt;So your :&lt;SPAN&gt;only use SRAM_DTC, i.e. 512kB DTCM and 0kB ITCM and 0kB OCRAM.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;It is not supported.&lt;/P&gt;
&lt;P&gt;Please choose other configuration, please also note:&lt;/P&gt;
&lt;P&gt;The Arm Cortex-M7 specifications require the size of ITCM/DTCM to be a power-of-two number, which can conflict with the FlexRAM&lt;BR /&gt;configuration capability (see configurations 7, 10, 11 in Table 1).&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Wish it helps you!&lt;/P&gt;
&lt;P&gt;Kerry&lt;/P&gt;</description>
      <pubDate>Wed, 23 Jun 2021 07:01:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1296609#M175903</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2021-06-23T07:01:05Z</dc:date>
    </item>
    <item>
      <title>Re: RT1170 EVK FLexRAM allocation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1296814#M175923</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/60336"&gt;@kerryzhou&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The RT 1176 always has OCRAM besides the flexram. Default configuration of the flexram is 256kB DTCM, 256kB ITCM and 0kB OCRAM. Is there more information specific to the RT 1176, because the process described in AN12077 if not working for us.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Kind regards,&lt;/P&gt;&lt;P&gt;John&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 23 Jun 2021 10:38:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1296814#M175923</guid>
      <dc:creator>johnvanmaanen</dc:creator>
      <dc:date>2021-06-23T10:38:27Z</dc:date>
    </item>
    <item>
      <title>Re: RT1170 EVK FLexRAM allocation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1296825#M175925</link>
      <description>&lt;P&gt;Thanks for your nitification!&lt;/P&gt;
&lt;P&gt;Another factor: flashloader .cfx put in the memory whichyou have disabled!&lt;/P&gt;
&lt;P&gt;&amp;nbsp; &amp;nbsp;Please don't worry, tomorrow, I will test your situation on my side directly, then give you feedback!&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Please keep patient!&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Kerry&lt;/P&gt;</description>
      <pubDate>Wed, 23 Jun 2021 11:07:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1296825#M175925</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2021-06-23T11:07:47Z</dc:date>
    </item>
    <item>
      <title>Re: RT1170 EVK FLexRAM allocation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1297903#M176024</link>
      <description>&lt;P&gt;Hello John,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I was discussing this internally with Kerry, and there are other things to take into consideration. Keep in mind that the community document was made for the RT10xx parts. The steps for the RT1170 are not the same.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;In the RT1170, you don't need to modify the file&amp;nbsp;fsl_flexspi_nor_boot.c. Please delete the line of code where you declared the ResetISR as extern and uncomment the line on&amp;nbsp;fsl_flexspi_nor_boot.h. This step only applies to the RT10xx parts.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;You also need to reallocate the stack pointer.&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;As I mentioned in the community document, t&lt;/SPAN&gt;&lt;SPAN&gt;here are lots of dangerous areas in reconfiguring the FlexRAM in code. It pretty much all boils down to the fact that any code/data/stack information written to the RAM can end up changing location during the reallocation.&amp;nbsp;To overcome this you'll need to place the stack at the start of the DTCM memory and change the size. This applies to all the RT parts. I'm working on updating the community document to add this information.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-center" image-alt="victorjimenez_0-1624557596640.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/147924i4FCA24B0B56622DE/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victorjimenez_0-1624557596640.png" alt="victorjimenez_0-1624557596640.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;After doing this you also have to add a couple of instructions inside the reset handler to reallocate the SP. Here are all the instructions that you need.&amp;nbsp;&lt;/P&gt;
&lt;LI-CODE lang="c"&gt;    /* Reallocating the FlexRAM */
    __asm (".syntax unified\n"

    		"LDR R0, =0x20001fff\n" //Reallocating the stack pointer
    		"MSR MSP,R0\n"

    		"LDR R0, =0x400e4044\n"//Address of register IOMUXC_GPR_GPR17
    		"LDR R1, =0x0000aaaa\n"//FlexRAM configuration DTC = 265KB, ITC = 128KB, OC = 128KB
    		"STR R1,[R0]\n"

    	    "LDR R0, =0x400e4048\n"//Address of register IOMUXC_GPR_GPR18
    	    "LDR R1, =0x0000aaaa\n"//FlexRAM configuration DTC = 265KB, ITC = 128KB, OC = 128KB
    	    "STR R1,[R0]\n"

    		"LDR R0,=0x400e4040\n"//Address of register IOMUXC_GPR_GPR16
    		"LDR R1,[R0]\n"
    		"ORR R1,R1,#4\n"//The 4 corresponds to setting the FLEXRAM_BANK_CFG_SEL bit in register IOMUXC_GPR_GPR16
    		"STR R1,[R0]\n"

    ".syntax divided\n");

    __asm volatile ("MSR MSP, %0" : : "r" (&amp;amp;_vStackTop) : );&lt;/LI-CODE&gt;
&lt;P&gt;You need to add these instructions right after disabling the interrupts inside the ResetISR.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;As Kerry mentioned to you already, you also need to modify the connect script to match the new value of the FlexRAM. I will add this in the community document as well since this applies to all the RT parts.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The changes that you made in the MCU settings and the MPU are correct. I made some tests on my end, and I was able to debug this without problems.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Victor&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 24 Jun 2021 18:06:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1297903#M176024</guid>
      <dc:creator>victorjimenez</dc:creator>
      <dc:date>2021-06-24T18:06:56Z</dc:date>
    </item>
    <item>
      <title>Re: RT1170 EVK FLexRAM allocation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1298507#M176057</link>
      <description>&lt;P&gt;Thank you for the responses.&lt;BR /&gt;&lt;BR /&gt;I have tried all the above suggestions. It seems that moving the stack pointer to the start of the DTCM memory solved the problem. However, a new problem now is that I cannot debug the board more than once during its power cycle, i.e if I am doing the following it works: build&amp;nbsp; -&amp;gt; debug (this works) -&amp;gt; terminate debug session, build -&amp;gt; debug -&amp;gt; error window. I then need to switch the board on and off to get this error window to dissapear: build -&amp;gt; debug -&amp;gt;&amp;nbsp; terminate debug session -&amp;gt; switch board off -&amp;gt; switch board on -&amp;gt; build -&amp;gt; debug -&amp;gt; works.&lt;/P&gt;&lt;P&gt;Pressing the reset button between debug sessions did seem to rid me of turning the board on and off again, but only for single core projects. When I try to do a multicore example, such as the&amp;nbsp;&lt;SPAN&gt;rpmsg_lite_pingpong_rtos example, and I use the above flexram configurtation, the 'reset' or 'turn-off and off' method does not solve a problem since a new error window occurs:&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Screenshot.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/148059i701101802787DF6D/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Screenshot.png" alt="Screenshot.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt; This error can only be fixed if I mass erase the board using the GUI flash tool. Clearly there is a bigger underlying problem here. Especially the flexram configuration of the M7 calling the M4.&lt;BR /&gt;&lt;BR /&gt;Thank you for your responses and assistance so far.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 25 Jun 2021 14:32:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1298507#M176057</guid>
      <dc:creator>dloub</dc:creator>
      <dc:date>2021-06-25T14:32:26Z</dc:date>
    </item>
    <item>
      <title>Re: RT1170 EVK FLexRAM allocation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1299298#M176132</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hello John,&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;I made some tests on my end, and I wasn't able to replicate the behavior that you mentioned. So, this has nothing to do with the reconfiguration of the FlexRAM through software. In the past when I have seen this type of behavior is normally because of a misconfiguration of a clock or because the application is trying to access an address of the memory that doesn't exist.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Regards,&lt;BR /&gt;Victor&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 29 Jun 2021 00:25:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1299298#M176132</guid>
      <dc:creator>victorjimenez</dc:creator>
      <dc:date>2021-06-29T00:25:11Z</dc:date>
    </item>
    <item>
      <title>Re: RT1170 EVK FLexRAM allocation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1299433#M176157</link>
      <description>&lt;P&gt;Hello Victor,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for your time. We will look into it further. It is strange that we have the problems with a demo project, where we only change the FlexRAM configuration. Did you work on the document about configuring the FlexRAM on the RT 1176?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Kind regards,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;John&lt;/P&gt;</description>
      <pubDate>Tue, 29 Jun 2021 05:59:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1299433#M176157</guid>
      <dc:creator>johnvanmaanen</dc:creator>
      <dc:date>2021-06-29T05:59:52Z</dc:date>
    </item>
    <item>
      <title>Re: RT1170 EVK FLexRAM allocation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1302612#M176428</link>
      <description>&lt;P&gt;Hello John,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I'm working on making the proper changes in my community document. Are you still facing the same behavior? If you make these changes in a non-multi-core project, do you face the same behavior?&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Victor&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 05 Jul 2021 23:57:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1302612#M176428</guid>
      <dc:creator>victorjimenez</dc:creator>
      <dc:date>2021-07-05T23:57:01Z</dc:date>
    </item>
    <item>
      <title>Re: RT1170 EVK FLexRAM allocation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1362332#M182193</link>
      <description>&lt;P&gt;Hello Kerry,&lt;/P&gt;&lt;P&gt;It's been a while since your last message. As we only changed the size of the memory after flashing (from our own code), we didn't have problems with flashing. Up to now.&amp;nbsp;&lt;/P&gt;&lt;P&gt;We used the eFuses to reconfigure the memory now and are not able to program the flash anymore. You mentioned that the flashloader uses ITC. Do you have more information about this? Is there a way to program the fuses for 512kB DTC and stil being able to program the flash memory?&lt;/P&gt;&lt;P&gt;Kind regards,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;John&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;John&lt;/P&gt;</description>
      <pubDate>Wed, 27 Oct 2021 09:24:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/1362332#M182193</guid>
      <dc:creator>johnvanmaanen</dc:creator>
      <dc:date>2021-10-27T09:24:51Z</dc:date>
    </item>
    <item>
      <title>Re: RT1170 EVK FLexRAM allocation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/2100683#M237400</link>
      <description>&lt;P class=""&gt;Hi Victor,&lt;/P&gt;&lt;P class=""&gt;Thank you very much for your detailed explanation.&lt;/P&gt;&lt;P class=""&gt;You mentioned you're currently updating the community document to include the FlexRAM reallocation, stack pointer adjustments, and the connect script changes. When it's available, could you please share the link or let me know where I can find it?&lt;/P&gt;&lt;P class=""&gt;That would be very helpful as I continue working on my setup.&lt;/P&gt;&lt;P class=""&gt;Best regards,&lt;BR /&gt;Mounsef&lt;/P&gt;</description>
      <pubDate>Tue, 20 May 2025 12:22:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/2100683#M237400</guid>
      <dc:creator>mounsef</dc:creator>
      <dc:date>2025-05-20T12:22:17Z</dc:date>
    </item>
    <item>
      <title>Re: RT1170 EVK FLexRAM allocation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/2100718#M237403</link>
      <description>&lt;P&gt;Thank you for sharing your experience. If you've managed to solve the issue, could you kindly share the final solution with us?&lt;/P&gt;</description>
      <pubDate>Tue, 20 May 2025 13:36:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/2100718#M237403</guid>
      <dc:creator>mounsef</dc:creator>
      <dc:date>2025-05-20T13:36:49Z</dc:date>
    </item>
    <item>
      <title>Re: RT1170 EVK FLexRAM allocation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/2100719#M237404</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/186535"&gt;@dloub&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Thank you for sharing your experience. If you've managed to solve the issue, could you kindly share the final solution with us?&lt;/P&gt;</description>
      <pubDate>Tue, 20 May 2025 13:40:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT1170-EVK-FLexRAM-allocation/m-p/2100719#M237404</guid>
      <dc:creator>mounsef</dc:creator>
      <dc:date>2025-05-20T13:40:49Z</dc:date>
    </item>
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