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    <title>topic Re: 8MPLUSLPD4-CPU LPDDR4 CKE Connection in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/8MPLUSLPD4-CPU-LPDDR4-CKE-Connection/m-p/1299662#M176184</link>
    <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/188492"&gt;@shimpei_sonoda&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;DRAM_CKE0_A corresponds DRAM_nCS0_A;&lt;BR /&gt;DRAM_CKE1_A corresponds DRAM_nCS1_A.&lt;/P&gt;
&lt;P&gt;&amp;nbsp; Data lanes swapping are not affected here.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
    <pubDate>Tue, 29 Jun 2021 11:30:46 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2021-06-29T11:30:46Z</dc:date>
    <item>
      <title>8MPLUSLPD4-CPU LPDDR4 CKE Connection</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/8MPLUSLPD4-CPU-LPDDR4-CKE-Connection/m-p/1299563#M176172</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;I designed the new product&amp;nbsp;with reference to the i.MX 8M Plus evaluation board "8MPLUSLPD4-CPU".&amp;nbsp; The file name is SPF-46368_A3.pdf.&lt;/P&gt;&lt;P&gt;In "8MPLUSLPD4-CPU", the Data signals of the LPDDR4 Ch.A output by the SoC are byte-swapped and connected to the DRAM. However, the CKE signals are not swapped. Should the CKEs be swapped?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for your reply.&lt;/P&gt;</description>
      <pubDate>Tue, 29 Jun 2021 08:54:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/8MPLUSLPD4-CPU-LPDDR4-CKE-Connection/m-p/1299563#M176172</guid>
      <dc:creator>shimpei_sonoda</dc:creator>
      <dc:date>2021-06-29T08:54:43Z</dc:date>
    </item>
    <item>
      <title>Re: 8MPLUSLPD4-CPU LPDDR4 CKE Connection</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/8MPLUSLPD4-CPU-LPDDR4-CKE-Connection/m-p/1299662#M176184</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/188492"&gt;@shimpei_sonoda&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;DRAM_CKE0_A corresponds DRAM_nCS0_A;&lt;BR /&gt;DRAM_CKE1_A corresponds DRAM_nCS1_A.&lt;/P&gt;
&lt;P&gt;&amp;nbsp; Data lanes swapping are not affected here.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Tue, 29 Jun 2021 11:30:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/8MPLUSLPD4-CPU-LPDDR4-CKE-Connection/m-p/1299662#M176184</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2021-06-29T11:30:46Z</dc:date>
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