i.MX ProcessorsのトピックRe: i.MX8QXP Pinmux problem with SPDIF0_RX/TX

i.MX8QXP Pinmux problem with SPDIF0_RX/TX

mod42 — Thu, 22 Apr 2021 12:58:27 GMT

We have a custom iMX8XQP board where we want to use the pads SPDIF0_RX / SPDIF0_TX as GPIOs (LSIO_GPIO0_IO10 / LSIO_GPIO0_IO11). I added the following entries to the pinctrl_hog

IMX8QXP_SPDIF0_RX_LSIO_GPIO0_IO10 0x00000041 IMX8QXP_SPDIF0_TX_LSIO_GPIO0_IO11 0x00000041

and test the GPIOs through sysfs. The gpios are exported correctly and I can use the files in sysfs but the corresponding pins are always low. I used this approach with a couple of other GPIOs and there it works as expected. Is there anything special about these two pads?

Re: i.MX8QXP Pinmux problem with SPDIF0_RX/TX

igorpadykov — Fri, 23 Apr 2021 00:41:49 GMT

Hi Matthias

as these pads are dual voltage pads one can try to add GPIORHB setting, described

in sect.9.2.5.1.75 IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB (IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB)

i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual
as in example :
https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi?h=imx_5.4.70_2.3.0

Best regards
igor

Re: i.MX8QXP Pinmux problem with SPDIF0_RX/TX

mod42 — Wed, 23 Jun 2021 06:12:48 GMT

Sorry for the late replay. Adding this

IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0

to the device tree node pinctrl_hog: hoggrp did the trick even it is not clear to me what the settings are changing. Setting bits 0 and 2 from field READ_NASRC which is not documented.