https://community.nxp.com/t5/i-MX-Processors/I-MX8M-Pluse-LPDDR4-Bit-swapping/m-p/1280138#M174371 <P><a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/165160">@mark_kim</a>&nbsp;<BR />Hello,</P> <P>&nbsp;&nbsp; Correct - "DRAM_DQ of I.MX8 can be routed to any data pin of LPDDR4 within a Byte lane".</P> <P>Regards,<BR />Yuri.</P> Fri, 21 May 2021 06:23:44 GMT Yuri 2021-05-21T06:23:44Z https://community.nxp.com/t5/i-MX-Processors/I-MX8M-Pluse-LPDDR4-Bit-swapping/m-p/1280111#M174364 <P>Dear</P><P>Could you confirm if there is any restriction for bit-swapping on LPDD4?</P><P>From the Hardware Developer's guide, Regarding LPDDR4 routing, I found " Bit swapping within each slice/byte lane is Ok".</P><P>What I undersande it is that DRAM_DQ of I.MX8 can be routed to any data pin of LPDDR4 within a Byte lane. Let me make example like DRAM_DQ01 rounted to DQ7(LPDDR4).</P><P>Aa far as I remember, a Certain NXP processor limited bit swapping within a nibble ( 4-bit lane).</P><P>I just make sure of what I understand.</P><P>I appreciate your help in advance.</P><P>thank you</P><P>Best Regards</P><P>Mark Kim</P> Fri, 21 May 2021 05:18:51 GMT https://community.nxp.com/t5/i-MX-Processors/I-MX8M-Pluse-LPDDR4-Bit-swapping/m-p/1280111#M174364 mark_kim 2021-05-21T05:18:51Z https://community.nxp.com/t5/i-MX-Processors/I-MX8M-Pluse-LPDDR4-Bit-swapping/m-p/1280138#M174371 <P><a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/165160">@mark_kim</a>&nbsp;<BR />Hello,</P> <P>&nbsp;&nbsp; Correct - "DRAM_DQ of I.MX8 can be routed to any data pin of LPDDR4 within a Byte lane".</P> <P>Regards,<BR />Yuri.</P> Fri, 21 May 2021 06:23:44 GMT https://community.nxp.com/t5/i-MX-Processors/I-MX8M-Pluse-LPDDR4-Bit-swapping/m-p/1280138#M174371 Yuri 2021-05-21T06:23:44Z