DDR3 routing, length matching

celiley — Sat, 15 May 2021 14:56:12 GMT

Hello,

There is a point I'm not sure about DDR3 routing. I'm following "Hardware Development Guide for
i.MX 6Quad" and this document says that the address signals must match 25 mils. When calculating the length of each signal, must we add the vias' length in the z direction to the total length? In my design, each address signal has the same number of vias but I drew some of the signals on different intermediate layers. When I add the depth of the via to the total length, there is a difference of about 150 mils. What do you suggest about it, what is the correct calculation in DDR3 routing?

Thanks, regards,

Celile

Re: DDR3 routing, length matching

igorpadykov — Mon, 17 May 2021 00:39:35 GMT

Hi Celile

yes vias length must be added to calculation. In general also may be recommended to perform

ibis modelling.

Best regards
igor

Re: DDR3 routing, length matching

celiley — Mon, 17 May 2021 05:11:33 GMT

Thank you @igorpadykov

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DDR3 routing, length matching

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Re: DDR3 routing, length matching