https://community.nxp.com/t5/i-MX-Processors/iMX6DL-MMU-setup/m-p/1276031#M173962 <P>Hi Micah</P> <P>&nbsp;</P> <P>one can try below patch</P> <P><A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Enabling-MMU-and-Caches-on-i-MX6-Series-Platform-SDK/ta-p/1108712" target="_blank">https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Enabling-MMU-and-Caches-on-i-MX6-Series-Platform-SDK/ta-p/1108712</A></P> <P>&nbsp;</P> <P>Best regards<BR />igor</P> Thu, 13 May 2021 00:31:43 GMT igorpadykov 2021-05-13T00:31:43Z https://community.nxp.com/t5/i-MX-Processors/iMX6DL-MMU-setup/m-p/1275830#M173947 <P>Hello I've starting working with the IMX6 dual lite board. My company runs all our applications with a bare metal implementation. I've gotten both core running but core 1 is extremely slow due to MMU not being set up. If I just try and copy what was done with the single core the processor crashes or I get undefined behavior. Does anyone know how to correctly setup the memory to separate core 0 from core 1 and also have a shared memory region. We would need to run this in AMP implantation as well.<BR /><BR />Thank you,<BR />Micah</P> Wed, 12 May 2021 18:06:09 GMT https://community.nxp.com/t5/i-MX-Processors/iMX6DL-MMU-setup/m-p/1275830#M173947 mjrudy 2021-05-12T18:06:09Z https://community.nxp.com/t5/i-MX-Processors/iMX6DL-MMU-setup/m-p/1276031#M173962 <P>Hi Micah</P> <P>&nbsp;</P> <P>one can try below patch</P> <P><A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Enabling-MMU-and-Caches-on-i-MX6-Series-Platform-SDK/ta-p/1108712" target="_blank">https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Enabling-MMU-and-Caches-on-i-MX6-Series-Platform-SDK/ta-p/1108712</A></P> <P>&nbsp;</P> <P>Best regards<BR />igor</P> Thu, 13 May 2021 00:31:43 GMT https://community.nxp.com/t5/i-MX-Processors/iMX6DL-MMU-setup/m-p/1276031#M173962 igorpadykov 2021-05-13T00:31:43Z