topic Re: IMX8MQ mipi-csi2 capture timeout in i.MX Processors

IMX8MQ mipi-csi2 capture timeout

Timothy_Jr_BB — Thu, 06 May 2021 07:00:15 GMT

Hi, Experts

We are now working on a third-party demo board kit of IMX8MQ, and trying to capture images from MIPI-CSI2 sensor.

We configured both the sensor and MIPI controller to 2 LANES mode, 800Mbps mode, and 8bits raw pixel format. User APP is modified from capture-example.c of V4L2.

The result is always "select timeout".

After stream on, I have checked the clock and data on Lanes, which are all correct, and sensor feedback with no error.

Following is the dumped register from MIPI controller and CSI bridge after hang on:

CSI mipi_controller Register 0x0100 value is 0x00000001.
CSI mipi_controller Register 0x0104 value is 0x0000000c.
CSI mipi_controller Register 0x0108 value is 0x00000000.
CSI mipi_controller Register 0x010c value is 0x00000008.
CSI mipi_controller Register 0x0110 value is 0x000001ff.
CSI mipi_controller Register 0x0114 value is 0x00000000.
CSI mipi_controller Register 0x0118 value is 0x00000000.
CSI mipi_controller Register 0x011c value is 0x00000000.
CSI mipi_controller Register 0x0120 value is 0x00000000.
CSI mipi_controller Register 0x0124 value is 0x00000000.
CSI mipi_controller Register 0x0128 value is 0x00000000.
CSI mipi_controller Register 0x012c value is 0x00000000.
CSI mipi_controller Register 0x0130 value is 0x00000000.
CSI mipi_controller Register 0x0188 value is 0x00000040.
CSI mipi_controller Register 0x018c value is 0x00000000.
CSI mipi_controller Register 0x0190 value is 0x00000000.
CSI mipi_controller Register 0x0194 value is 0x00000000.
CSI mipi_controller Register 0x0198 value is 0x00000000.
CSI bridge Register 0x00 value is 0x011b0902.
CSI bridge Register 0x04 value is 0xc0000000.
CSI bridge Register 0x08 value is 0x000010a0.
CSI bridge Register 0x0c value is 0x00000000.
CSI bridge Register 0x10 value is 0x00000000.
CSI bridge Register 0x14 value is 0x00009600.
CSI bridge Register 0x18 value is 0x80004000.
CSI bridge Register 0x1c value is 0x00000000.
CSI bridge Register 0x20 value is 0x00000000.
CSI bridge Register 0x24 value is 0x00000000.
CSI bridge Register 0x28 value is 0x6a300000.
CSI bridge Register 0x2c value is 0x6a800000.
CSI bridge Register 0x30 value is 0x00000000.
CSI bridge Register 0x34 value is 0x0a000790.
CSI bridge Register 0x48 value is 0xd44ad030.
CSI bridge Register 0x4c value is 0x00000000.

Also no error reported. The CSI_CSIRXCNT (CSI bridge Register 0x14) shows about 0x9600 words has been transferred. But I cannot find any clue from this.

Does anyone have some suggestion on this ?

Re: IMX8MQ mipi-csi2 capture timeout

igorpadykov — Thu, 06 May 2021 10:31:55 GMT

Hi Chenguang

for hanging issue one can look at

https://community.nxp.com/t5/i-MX-Processors/RX-fifo-overflow-on-MIPI-CSI2-i-MX8MQ/m-p/1087697?commentID=1306949#comment-1306949

Best regards
igor

Re: IMX8MQ mipi-csi2 capture timeout

Timothy_Jr_BB — Sat, 08 May 2021 07:00:07 GMT

@igorpadykov

Thanks for your reply.

Unluckily, my problem is not overflow, because CSICR19(0x4C) register is always 0.

Now I have set format to 640x480 instead of 5M pixels, but the result is the same, "select timeout".

Error shows in CSI mipi-controller 0x0118 and 0x011C register, both of them is 0x3, that is ErrSotHS and ErrSotSync_HS. And also 0x108 value is 0x1, means 2 bit ECC error has occured.

Following is register dump:

CSI mipi_controller Register 0x0100 value is 0x00000001.
CSI mipi_controller Register 0x0104 value is 0x0000000c.
CSI mipi_controller Register 0x0108 value is 0x00000001.
CSI mipi_controller Register 0x010c value is 0x0000003c.
CSI mipi_controller Register 0x0110 value is 0x000001ff.
CSI mipi_controller Register 0x0114 value is 0x00000000.
CSI mipi_controller Register 0x0118 value is 0x00000003.
CSI mipi_controller Register 0x011c value is 0x00000003.
CSI mipi_controller Register 0x0120 value is 0x00000000.
CSI mipi_controller Register 0x0124 value is 0x00000000.
CSI mipi_controller Register 0x0128 value is 0x00000000.
CSI mipi_controller Register 0x012c value is 0x00000000.
CSI mipi_controller Register 0x0130 value is 0x00000000.
CSI mipi_controller Register 0x0188 value is 0x00000040.
CSI mipi_controller Register 0x018c value is 0x00000000.
CSI mipi_controller Register 0x0190 value is 0x00000000.
CSI mipi_controller Register 0x0194 value is 0x00000000.
CSI mipi_controller Register 0x0198 value is 0x00000000.
CSI bridge Register 0x00 value is 0x011b0902.
CSI bridge Register 0x04 value is 0xc0000000.
CSI bridge Register 0x08 value is 0x000010a0.
CSI bridge Register 0x0c value is 0x00000000.
CSI bridge Register 0x10 value is 0x00000000.
CSI bridge Register 0x14 value is 0x00009600.
CSI bridge Register 0x18 value is 0x80004000.
CSI bridge Register 0x1c value is 0x00000000.
CSI bridge Register 0x20 value is 0x00000000.
CSI bridge Register 0x24 value is 0x00000000.
CSI bridge Register 0x28 value is 0x6a300000.
CSI bridge Register 0x2c value is 0x6a380000.
CSI bridge Register 0x30 value is 0x00000000.
CSI bridge Register 0x34 value is 0x028001e0.
CSI bridge Register 0x48 value is 0xd44ad030.
CSI bridge Register 0x4c value is 0x00000000.

Re: IMX8MQ mipi-csi2 capture timeout

igorpadykov — Sat, 08 May 2021 10:27:47 GMT

one can check discussion below in particular HS_SETTLE settings :

https://community.nxp.com/t5/i-MX-Processors/iMX8M-MIPI-CSI-4-lane-configuration/m-p/875755

Best regards
igor

Re: IMX8MQ mipi-csi2 capture timeout

Timothy_Jr_BB — Mon, 10 May 2021 11:08:13 GMT

hi, Igor

I have checked the topic https://community.nxp.com/t5/i-MX-Processors/Explenation-for-HS-SETTLE-parameter-in-MIPI-CSI-D-PHY-registers/m-p/764265, and still unclear for me.

According to Qiangli, for IMX8MQ, the HS_SETTLE should be calculated followed table35, but unclear, how to decide the frequency of RxClkInEsc ? Is that the 'IMX8MQ_CLK_CSI1_ESC' in the device tree ?

And our MIPI is 400MHz, 2 lanes, 8-bit raw format, and how to set the assigned-clock-rates in following device tree ?

mipi_csi_1: mipi_csi1@30a70000 {
compatible = "fsl,mxc-mipi-csi2_yav";
reg = <0x0 0x30a70000 0x0 0x1000>; /* MIPI CSI1 Controller base addr */
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_CSI1_CORE>,
<&clk IMX8MQ_CLK_CSI1_ESC>,
<&clk IMX8MQ_CLK_CSI1_PHY_REF>;
clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
<&clk IMX8MQ_CLK_CSI1_PHY_REF>,
<&clk IMX8MQ_CLK_CSI1_ESC>;
assigned-clock-rates = <133000000>, <100000000>, <66000000>;
power-domains = <&mipi_csi1_pd>;
csis-phy-reset = <&src 0x4c 7>;
phy-gpr = <&gpr 0x88>;
status = "disabled";
};

Re: IMX8MQ mipi-csi2 capture timeout

Timothy_Jr_BB — Wed, 12 May 2021 04:00:01 GMT

@igorpadykov

After I configured the CSI_CSICR18 MASK_OPTION BIT[19:18] to 00 (2'b10 as before), then the select timeout will not happen.

And also , the CSI_RFIFO reg is no longer 0, the FIFO_level register is 0x10 ,which means pixel data have been received in FIFO.

But the saved image size is 0 bytes.

Could you explain the function of MASK_OPTION ? That's helpful for further debug.

thanks!

Re: IMX8MQ mipi-csi2 capture timeout

Timothy_Jr_BB — Wed, 12 May 2021 08:14:12 GMT

Hi, Again

I also have question on CSI_CSIFBUF_PARA register setting.

To my application, image has no interlaced mode, so the driver (mx6s_capture.c) set to 0.

But according to IM8M RM, this register should be set to show how many double words to skip before starting to write the next row of the image.

I don't know whether it is required to set this , if yes, how to decide the FBUF_STRIDE value. Our image frame is as below figure: