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    <title>i.MX ProcessorsのトピックRe: i.MX8MP TSN implementation details</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-TSN-implementation-details/m-p/1271718#M173569</link>
    <description>&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;thanks for the link. I've analyzed it and it explains the software setup for the AVB/TSN demo.&lt;/P&gt;&lt;P&gt;I'm talking about the hardware requirement of the TSN ethernet interface. On the EVK reference schematic there is no hardware difference between EHT1 and ETH2, but only ETH2 supports the TSN.&lt;/P&gt;&lt;P&gt;Could you confirm that the TSN functionality has no dependence on the ethernet PHY used?&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Matteo Silotto&lt;/P&gt;</description>
    <pubDate>Fri, 07 May 2021 07:13:46 GMT</pubDate>
    <dc:creator>matteo_silotto</dc:creator>
    <dc:date>2021-05-07T07:13:46Z</dc:date>
    <item>
      <title>i.MX8MP TSN implementation details</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-TSN-implementation-details/m-p/1270251#M173403</link>
      <description>&lt;P&gt;Hi support team,&lt;/P&gt;&lt;P&gt;on&amp;nbsp;i.MX8MPlus only one ethernet port supports TSN (ENET2_TSN).&lt;/P&gt;&lt;P&gt;In the EVK reference design, you do not use a PHY with a hardware timestamp nor other additional signals (eg. Start-of-frame detect) from the PHY to the MAC.&lt;/P&gt;&lt;P&gt;So, could you confirm that the TSN implementation on i.MX8MPlus is a pure software or MAC level implementation? And does it not require a specific PHY?&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;</description>
      <pubDate>Thu, 29 Apr 2021 09:42:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-TSN-implementation-details/m-p/1270251#M173403</guid>
      <dc:creator>matteo_silotto</dc:creator>
      <dc:date>2021-04-29T09:42:43Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8MP TSN implementation details</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-TSN-implementation-details/m-p/1270795#M173456</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/152289"&gt;@matteo_silotto&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp; Customers can refer to the following demo:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/AVB-TSN-demo-on-i-MX8MP/ta-p/1123791" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/AVB-TSN-demo-on-i-MX8MP/ta-p/1123791&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Fri, 30 Apr 2021 09:39:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-TSN-implementation-details/m-p/1270795#M173456</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2021-04-30T09:39:43Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8MP TSN implementation details</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-TSN-implementation-details/m-p/1271718#M173569</link>
      <description>&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;thanks for the link. I've analyzed it and it explains the software setup for the AVB/TSN demo.&lt;/P&gt;&lt;P&gt;I'm talking about the hardware requirement of the TSN ethernet interface. On the EVK reference schematic there is no hardware difference between EHT1 and ETH2, but only ETH2 supports the TSN.&lt;/P&gt;&lt;P&gt;Could you confirm that the TSN functionality has no dependence on the ethernet PHY used?&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Matteo Silotto&lt;/P&gt;</description>
      <pubDate>Fri, 07 May 2021 07:13:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-TSN-implementation-details/m-p/1271718#M173569</guid>
      <dc:creator>matteo_silotto</dc:creator>
      <dc:date>2021-05-07T07:13:46Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8MP TSN implementation details</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-TSN-implementation-details/m-p/1273471#M173720</link>
      <description>&lt;P&gt;Hi Yuri,&lt;/P&gt;&lt;P&gt;thanks for the link. I've analyzed it and it explains the software setup for the AVB/TSN demo.&lt;/P&gt;&lt;P&gt;I'm talking about the hardware requirement of the TSN ethernet interface. On the EVK reference schematic there is no hardware difference between EHT1 and ETH2, but only ETH2 supports the TSN.&lt;/P&gt;&lt;P&gt;Could you confirm that the TSN functionality has no dependence on the ethernet PHY used?&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Matteo Silotto&lt;/P&gt;</description>
      <pubDate>Fri, 07 May 2021 07:12:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-TSN-implementation-details/m-p/1273471#M173720</guid>
      <dc:creator>matteo_silotto</dc:creator>
      <dc:date>2021-05-07T07:12:49Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8MP TSN implementation details</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-TSN-implementation-details/m-p/1276849#M174052</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/152289"&gt;@matteo_silotto&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; yes, " the TSN functionality has no dependence on the ethernet PHY used".&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Fri, 14 May 2021 07:43:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-TSN-implementation-details/m-p/1276849#M174052</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2021-05-14T07:43:41Z</dc:date>
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