<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: imx8 is compatible with two AHD conversion chips</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx8-is-compatible-with-two-AHD-conversion-chips/m-p/1271045#M173482</link>
    <description>&lt;P&gt;Hi Hongliang&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;for using both nvp6324 and tp2815 it is necessary to use two&amp;nbsp;mipi-csi ports as in example&lt;/P&gt;
&lt;P&gt;&lt;A href="https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts?h=imx_5.4.70_2.3.0" target="_blank"&gt;https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts?h=imx_5.4.70_2.3.0&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Nvp6324-driver-for-imx8qm/ta-p/1114616" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Nvp6324-driver-for-imx8qm/ta-p/1114616&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
    <pubDate>Sat, 01 May 2021 04:30:23 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2021-05-01T04:30:23Z</dc:date>
    <item>
      <title>imx8 is compatible with two AHD conversion chips</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8-is-compatible-with-two-AHD-conversion-chips/m-p/1270803#M173458</link>
      <description>&lt;P&gt;hi，&lt;/P&gt;&lt;P&gt;I want use AHD chip, nvp6324 or tp2815, In imx8 mipi csi0，How to configure the device tree。&lt;/P&gt;&lt;P&gt;/*add by shl*/&lt;BR /&gt;#if 1&lt;BR /&gt;&amp;amp;i2c_mipi_csi0 {&lt;BR /&gt;#address-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;#size-cells = &amp;lt;0&amp;gt;;&lt;BR /&gt;pinctrl-names = "default";&lt;BR /&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_i2c_mipi_csi0&amp;gt;;&lt;BR /&gt;clock-frequency = &amp;lt;100000&amp;gt;;&lt;BR /&gt;status = "okay";&lt;/P&gt;&lt;P&gt;//7bit addr&lt;BR /&gt;nvp6324_mipi@30 {&lt;BR /&gt;compatible = "nextchip,nvp6324_mipi";&lt;BR /&gt;reg = &amp;lt;0x30&amp;gt;;&lt;BR /&gt;pinctrl-names = "default";&lt;BR /&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_mipi_csi0&amp;gt;;&lt;BR /&gt;clocks = &amp;lt;&amp;amp;clk_dummy&amp;gt;;&lt;BR /&gt;clock-names = "capture_mclk";&lt;BR /&gt;mclk = &amp;lt;27000000&amp;gt;;&lt;BR /&gt;mclk_source = &amp;lt;0&amp;gt;;&lt;BR /&gt;virtual-channel;&lt;BR /&gt;pwn-gpios = &amp;lt;&amp;amp;lsio_gpio3 8 GPIO_ACTIVE_HIGH&amp;gt;;&lt;BR /&gt;status = "okay";&lt;/P&gt;&lt;P&gt;port {&lt;BR /&gt;nvp6324_0_ep: endpoint {&lt;BR /&gt;remote-endpoint = &amp;lt;&amp;amp;mipi_csi0_ep&amp;gt;;&lt;BR /&gt;data-lanes = &amp;lt;1 2 3 4&amp;gt;;&lt;BR /&gt;};&lt;BR /&gt;};&lt;BR /&gt;};&lt;BR /&gt;&lt;BR /&gt;//7bit addr&lt;BR /&gt;tp2815_mipi@44 {&lt;BR /&gt;compatible = "techpoint,tp2815_mipi";&lt;BR /&gt;reg = &amp;lt;0x44&amp;gt;;&lt;BR /&gt;pinctrl-names = "default";&lt;BR /&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_mipi_csi0&amp;gt;;&lt;BR /&gt;clocks = &amp;lt;&amp;amp;clk_dummy&amp;gt;;&lt;BR /&gt;clock-names = "capture_mclk";&lt;BR /&gt;mclk = &amp;lt;27000000&amp;gt;;&lt;BR /&gt;mclk_source = &amp;lt;0&amp;gt;;&lt;BR /&gt;virtual-channel;&lt;BR /&gt;irq-gpios = &amp;lt;&amp;amp;lsio_gpio3 7 GPIO_ACTIVE_HIGH&amp;gt;;&lt;BR /&gt;pwn-gpios = &amp;lt;&amp;amp;lsio_gpio3 8 GPIO_ACTIVE_HIGH&amp;gt;;&lt;BR /&gt;status = "disabled";&lt;/P&gt;&lt;P&gt;port {&lt;BR /&gt;tp2815_0_ep: endpoint {&lt;BR /&gt;remote-endpoint = &amp;lt;&amp;amp;mipi_csi0_ep&amp;gt;;&lt;BR /&gt;data-lanes = &amp;lt;1 2 3 4&amp;gt;;&lt;BR /&gt;};&lt;BR /&gt;};&lt;BR /&gt;};&lt;BR /&gt;/delete-node/ max9286_mipi@6a;&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&amp;amp;mipi_csi_0 {&lt;BR /&gt;#address-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;#size-cells = &amp;lt;0&amp;gt;;&lt;BR /&gt;virtual-channel;&lt;BR /&gt;status = "okay";&lt;/P&gt;&lt;P&gt;/* Camera 0 MIPI CSI-2 (CSIS0) tp2815_0_ep nvp6324_0_ep*/&lt;BR /&gt;port@0 {&lt;BR /&gt;reg = &amp;lt;0&amp;gt;;&lt;BR /&gt;mipi_csi0_ep: endpoint {&lt;BR /&gt;remote-endpoint = &amp;lt;&amp;amp;nvp6324_0_ep&amp;gt;;&lt;BR /&gt;data-lanes = &amp;lt;1 2 3 4&amp;gt;;&lt;BR /&gt;};&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;/*&lt;BR /&gt;port@1 {&lt;BR /&gt;reg = &amp;lt;1&amp;gt;;&lt;BR /&gt;mipi_csi0_ep: endpoint {&lt;BR /&gt;remote-endpoint = &amp;lt;&amp;amp;nvp6324_0_ep&amp;gt;;&lt;BR /&gt;data-lanes = &amp;lt;1 2 3 4&amp;gt;;&lt;BR /&gt;};&lt;BR /&gt;};&lt;BR /&gt;*/&lt;BR /&gt;};&lt;BR /&gt;#endif&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;</description>
      <pubDate>Fri, 30 Apr 2021 10:15:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8-is-compatible-with-two-AHD-conversion-chips/m-p/1270803#M173458</guid>
      <dc:creator>songhongliang</dc:creator>
      <dc:date>2021-04-30T10:15:19Z</dc:date>
    </item>
    <item>
      <title>Re: imx8 is compatible with two AHD conversion chips</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8-is-compatible-with-two-AHD-conversion-chips/m-p/1271045#M173482</link>
      <description>&lt;P&gt;Hi Hongliang&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;for using both nvp6324 and tp2815 it is necessary to use two&amp;nbsp;mipi-csi ports as in example&lt;/P&gt;
&lt;P&gt;&lt;A href="https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts?h=imx_5.4.70_2.3.0" target="_blank"&gt;https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640.dts?h=imx_5.4.70_2.3.0&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Nvp6324-driver-for-imx8qm/ta-p/1114616" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Nvp6324-driver-for-imx8qm/ta-p/1114616&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
      <pubDate>Sat, 01 May 2021 04:30:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8-is-compatible-with-two-AHD-conversion-chips/m-p/1271045#M173482</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2021-05-01T04:30:23Z</dc:date>
    </item>
    <item>
      <title>Re: imx8 is compatible with two AHD conversion chips</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8-is-compatible-with-two-AHD-conversion-chips/m-p/1272705#M173652</link>
      <description>&lt;P&gt;&lt;SPAN class="VIiyi"&gt;&lt;SPAN class="JLqJ4b ChMk0b"&gt;&lt;SPAN&gt;HI&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="VIiyi"&gt;&amp;nbsp;&lt;SPAN class="JLqJ4b ChMk0b"&gt;&lt;SPAN&gt;What I mean is that it is compatible with tp2815 and nvp6324 on CSI0. In fact, only one chip is used at a time. With a mirroring code, it can be compatible with two chips and automatically identify and load the driver.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="VIiyi"&gt;&lt;SPAN class="JLqJ4b ChMk0b"&gt;&lt;SPAN&gt;thanks&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 06 May 2021 06:18:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8-is-compatible-with-two-AHD-conversion-chips/m-p/1272705#M173652</guid>
      <dc:creator>songhongliang</dc:creator>
      <dc:date>2021-05-06T06:18:39Z</dc:date>
    </item>
  </channel>
</rss>

