mx6ull mdio problem

ValeriyUrmanov — Mon, 26 Apr 2021 10:52:08 GMT

i have MCIMX6Y0CVM05AA based board.

ethernet pins are reconfugured. I build last U-boot fomr denx. FEC did not see 88e6122 swith on address 02. I connected mdio analyzer and see all the packets in the bus are not correct.

&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "mii";
phy-handle = <&ethphy0>;
status = "okay";

mdio {
#address-cells = <1>;
#size-cells = <0>;

ethphy0: ethernet-phy@1 {
reg = <2>;
};
};

};

&iomuxc {
pinctrl-names = "default";
reg = <0x020e0000 0x4000>;

imx6ul-evk {

pinctrl_enet1: enet1grp {
fsl,pins = <

MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000010B0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000010B0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000010B0
MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x000010B0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000010B0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000010B0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000010B0
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x000010B0
MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x000010B0
MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x000010B0
MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x000010B0
MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x000010B0
MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x000010B0

>;
};

pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x000010B0
MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x000010B0
>;
};

i have working u-boot binary for this board, Mdio traffic is OK. but i need to recompile it.

Re: mx6ull mdio problem

Yuri — Tue, 27 Apr 2021 05:25:28 GMT

@ValeriyUrmanov
Hello,

Could You try NXP U-boot in order to analyze MDIO sources?
Use Chapter 3 (Porting U-Boot) of the Porting Guide.

https://www.nxp.com/docs/en/user-guide/IMX_PORTING_GUIDE.pdf

Regards,
Yuri.

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