topic Re: i.MX6Q, RGMII signal timimng in i.MX Processors

i.MX6Q, RGMII signal timimng

Aemj — Sun, 12 Jan 2014 08:55:53 GMT

Dear All,

I would like to ask about Figure54 ‘RGMII Receive Signal Timing Diagram Original’ in i.MX6DQ datasheet(IMX6DQCEC Rev2.3).

In my understanding,

TskewR represents the required delay of RXC signal on i.MX6 side for receiving data from PHY.

Am I correct?

Thanks,

Miyamoto

Re: i.MX6Q, RGMII signal timimng

Milco — Sun, 12 Jan 2014 11:39:56 GMT

Dear Miyamoto,

the figure 54 shows that you have to balance the TskewT and TskewR in order to have the correct Tsetup and Thold at receiver (i.MX6).

You need to write in the GiGABit PHY registers to obtain the proper delay.

Milco

Re: i.MX6Q, RGMII signal timimng

Aemj — Tue, 14 Jan 2014 06:20:40 GMT

Dear Milco,

I found RGMII specification from Internet.

http://www.hp.com/rnd/pdfs/RGMIIv2_0_final_hp.pdf

Can I understand as below?

(1)

The Tsetup and Thold you mentioned are the ones that are described in TABLE-2 in this document.

(2)

User needs to set TskewR to MAC (i.MX6 side) as a delay.

Am I correct?

Miyamoto

Re: i.MX6Q, RGMII signal timimng

Milco — Wed, 15 Jan 2014 07:59:03 GMT

Yes, you are correct, but the user needs to set the delay on PHY's registers.

I don't find i.Mx6 MAC no register dedicated at delay setup, usually the GIGABIT PHYs have internal registers writable by MDIO bus.

On my board, the correct timing at i.Mx6 side, was made by writing to the phy's registers.

Milco

Re: i.MX6Q, RGMII signal timimng

Aemj — Thu, 16 Jan 2014 05:25:56 GMT

Dear Milco,

Tanks for your reply.

My customer still has a question on this.

Can I understand as below?

i.MX6 will work fine if TskewR is set to the values of during 1nS and 2.6nS, which are written in i.MX6 datasheet as min and max values of TskewR.

Sorry for pushing you but the customer wants your answer asap.

BR,

Miyamoto

Re: i.MX6Q, RGMII signal timimng

Milco — Thu, 16 Jan 2014 17:27:57 GMT

Hi Miyamoto,

yes, is correct.

The clock period is 8 ns and so, the half period is 4 ns. Accordingly, the optimal delay should be about 2 ns (between 1ns and 2.6 ns written in i.MX6 datasheet).

User can set this delay by writing in the PHY's register, or by adding delay during the clock signal routing.

BR,

Milco