<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259651#M172357</link>
    <description>&lt;P&gt;for 4-lane and 2-lane settings, did you compare their log file? anything different? did you get the correct log file when you set the 4-lane? and your dts file is limited, so you can refer to the patch first then tell me the result&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 09 Apr 2021 11:41:15 GMT</pubDate>
    <dc:creator>joanxie</dc:creator>
    <dc:date>2021-04-09T11:41:15Z</dc:date>
    <item>
      <title>Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1236361#M170007</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I am using a 3rd-party ISP+Sensor combo with i.MX8M Mini and facing an issue when using 4-lane configuration.&lt;/P&gt;&lt;P&gt;When I use 1-lane or 2-lane, I am able to capture from camera successfully. But when I use 4-lanes, I am unable to capture anything. I have measured MIPI signals on all 4-lanes from sensor to IMX8MM and they are fine.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;1-lane DTS configuration:&lt;/STRONG&gt;&lt;BR /&gt;mipi1_sensor_ep: endpoint@1 {&lt;BR /&gt;remote-endpoint = &amp;lt;&amp;amp;camera&amp;gt;;&lt;BR /&gt;data-lanes = &amp;lt;1&amp;gt;;&lt;BR /&gt;csis-hs-settle = &amp;lt;13&amp;gt;;&lt;BR /&gt;csis-clk-settle = &amp;lt;2&amp;gt;;&lt;BR /&gt;csis-wclk;&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;2-lane DTS configuration:&lt;/STRONG&gt;&lt;BR /&gt;mipi1_sensor_ep: endpoint@1 {&lt;BR /&gt;remote-endpoint = &amp;lt;&amp;amp;camera&amp;gt;;&lt;BR /&gt;data-lanes = &amp;lt;2&amp;gt;;&lt;BR /&gt;csis-hs-settle = &amp;lt;13&amp;gt;;&lt;BR /&gt;csis-clk-settle = &amp;lt;2&amp;gt;;&lt;BR /&gt;csis-wclk;&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;4-lane DTS configuration:&lt;/STRONG&gt;&lt;BR /&gt;mipi1_sensor_ep: endpoint@1 {&lt;BR /&gt;remote-endpoint = &amp;lt;&amp;amp;camera&amp;gt;;&lt;BR /&gt;data-lanes = &amp;lt;1 2 3 4&amp;gt;;&lt;BR /&gt;csis-hs-settle = &amp;lt;13&amp;gt;;&lt;BR /&gt;csis-clk-settle = &amp;lt;2&amp;gt;;&lt;BR /&gt;csis-wclk;&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;I also tried to use "data-lanes = &amp;lt;4&amp;gt;", but got same issue.&lt;/P&gt;&lt;P&gt;This issue is reported in another post (link is below). The solution in that post is to use 1-lane only. But that solution is not feasible for me as I need to use higher resolution at later stage. I tried the other suggestions from this post but none of them worked.&lt;BR /&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/iMX8M-MIPI-CSI-4-lane-configuration/m-p/875755" target="_blank" rel="noopener"&gt;https://community.nxp.com/t5/i-MX-Processors/iMX8M-MIPI-CSI-4-lane-configuration/m-p/875755&lt;/A&gt;&lt;/P&gt;&lt;P&gt;Q1: Is 4-lane configuration validated on IMX8MM?&amp;nbsp;&lt;SPAN&gt;Any information about the use-case/testing done with 4 lanes will be appreciated.&lt;/SPAN&gt;?&lt;BR /&gt;Q2:&amp;nbsp;Is there a patch or changes needed to enable 4-lane configuration?&lt;BR /&gt;&lt;SPAN&gt;Q3: Any debug pointers to resolve this issue?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;BR /&gt;Naman&lt;/P&gt;</description>
      <pubDate>Thu, 25 Feb 2021 07:03:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1236361#M170007</guid>
      <dc:creator>namanthaker</dc:creator>
      <dc:date>2021-02-25T07:03:35Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1245189#M170813</link>
      <description>&lt;P&gt;what resolution and frame rate do you need to support? what bsp do you use? what clock frequency do you set ?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 13 Mar 2021 14:57:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1245189#M170813</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2021-03-13T14:57:20Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1245442#M170842</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/39586"&gt;@joanxie&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;I am using 1080p@30hz resolution on Yocto L5.4.47-2.2.0. This resolution is just for testing purpose, my actual use-case will be 5MP@30Hz.&lt;/P&gt;&lt;P&gt;I have not set any clock frequency for MIPI-CSI or MCLK in i.MX8MM. The MCLK (48MHz) is generated through external oscillator.&lt;/P&gt;&lt;P&gt;Attached dts file for reference.&lt;/P&gt;&lt;P&gt;Regards,&lt;BR /&gt;Naman&lt;/P&gt;</description>
      <pubDate>Mon, 15 Mar 2021 07:07:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1245442#M170842</guid>
      <dc:creator>namanthaker</dc:creator>
      <dc:date>2021-03-15T07:07:35Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1246889#M170959</link>
      <description>&lt;P&gt;what camera do you use? as I known, ov5640 only support 1-lane and 2-lane,1Gbps max per lane, so you need confirm your camera could support this first.&lt;/P&gt;</description>
      <pubDate>Wed, 17 Mar 2021 06:16:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1246889#M170959</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2021-03-17T06:16:42Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1247868#M171026</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/39586"&gt;@joanxie&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;I am using a 3rd Party Camera sensor and ISP combo. It does support MIPI 4-lane which I have tested and checked on its EVM.&lt;/P&gt;&lt;P&gt;When I am using 4-lane configuration, I am seeing MIPI signals on all 4 lanes and they are same as when using 2-lane configuration. So, I do not doubt the issue to be on the camera side.&lt;/P&gt;&lt;P&gt;Regards,&lt;BR /&gt;Naman&lt;/P&gt;</description>
      <pubDate>Thu, 18 Mar 2021 06:55:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1247868#M171026</guid>
      <dc:creator>namanthaker</dc:creator>
      <dc:date>2021-03-18T06:55:13Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1249318#M171179</link>
      <description>&lt;P&gt;first, you need confirm if your senor set 4-lane already, then tell me what data format you use? currently, development team validated &lt;A href="mailto:4k@30" target="_blank"&gt;4k@30&lt;/A&gt; yuv422 on imx8mm successfully, on dts settings are:&lt;BR /&gt;data-lanes = &amp;lt;4&amp;gt;;&lt;BR /&gt;csis-hs-settle = &amp;lt;13&amp;gt;;&lt;BR /&gt;csis-clk-settle = &amp;lt;2&amp;gt;;&lt;BR /&gt;&amp;nbsp;csis-wclk;&lt;/P&gt;</description>
      <pubDate>Mon, 22 Mar 2021 04:38:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1249318#M171179</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2021-03-22T04:38:11Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1249745#M171217</link>
      <description>&lt;P&gt;Yes, I have confirmed that the sensor is set at 4-lane configuration and I am trying to capture YUV422 (UYVY) format at &lt;A href="mailto:1080@30fps" target="_blank" rel="noopener"&gt;1080@30fps&lt;/A&gt;.&lt;/P&gt;</description>
      <pubDate>Mon, 22 Mar 2021 14:18:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1249745#M171217</guid>
      <dc:creator>namanthaker</dc:creator>
      <dc:date>2021-03-22T14:18:56Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1250294#M171271</link>
      <description>&lt;P&gt;try to enable double pixel mode in the mipi driver as below:&lt;/P&gt;
&lt;P&gt;add this in the drivers/media/platform/mxc/capture/mx6s_capture.c&lt;/P&gt;
&lt;P&gt;case V4L2_PIX_FMT_UYVY:&lt;BR /&gt;case V4L2_PIX_FMT_YUYV:&lt;BR /&gt;cr18 |= BIT_MIPI_DATA_FORMAT_YUV422_8B;&lt;BR /&gt;+ cr18 |= BIT_MIPI_DOUBLE_CMPNT;&lt;BR /&gt;break;&lt;/P&gt;
&lt;P&gt;in the drivers/media/platform/mxc/capture/mxc_mipi_csi.c:&lt;/P&gt;
&lt;P&gt;mipi_csis_formats[] = {&lt;BR /&gt;.fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,&lt;BR /&gt;.data_alignment = 16,&lt;BR /&gt;}, {&lt;BR /&gt;+ .code = MEDIA_BUS_FMT_UYVY8_2X8,&lt;BR /&gt;+ .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,&lt;BR /&gt;+ .data_alignment = 16,&lt;BR /&gt;+ }, {&lt;BR /&gt;.code = MEDIA_BUS_FMT_SBGGR8_1X8,&lt;BR /&gt;.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,&lt;BR /&gt;.data_alignment = 8,&lt;BR /&gt;@@ -486,6 +490,8 @@ static void __mipi_csis_set_format(struct csi_state *state)&lt;BR /&gt;/* Color format */&lt;BR /&gt;val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0);&lt;BR /&gt;val = (val &amp;amp; ~MIPI_CSIS_ISPCFG_FMT_MASK) | state-&amp;gt;csis_fmt-&amp;gt;fmt_reg;&lt;BR /&gt;+ val |= MIPI_CSIS_ISPCFG_DOUBLE_CMPNT;&lt;BR /&gt;+&lt;BR /&gt;mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);&lt;/P&gt;</description>
      <pubDate>Tue, 23 Mar 2021 09:23:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1250294#M171271</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2021-03-23T09:23:59Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1250496#M171289</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/39586"&gt;@joanxie&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;I tried the above suggested changes, but still unable to capture 4-lane data.&lt;/P&gt;&lt;P&gt;Regards,&lt;BR /&gt;Naman&lt;/P&gt;</description>
      <pubDate>Tue, 23 Mar 2021 14:08:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1250496#M171289</guid>
      <dc:creator>namanthaker</dc:creator>
      <dc:date>2021-03-23T14:08:39Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1253418#M171670</link>
      <description>&lt;P&gt;if you can get correct signal from 4lane by oscilloscope, you need to check csis-hs-settle=&amp;lt;13&amp;gt;; this is calculated by the bit rate per lane&lt;/P&gt;
&lt;DIV style="box-sizing: border-box; font-family: 'Segoe UI', system-ui, 'Apple Color Emoji', 'Segoe UI Emoji', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/How-to-compute-S-CLKSETTLECTL-value-for-MIPI-CSI-2-receiver-on-i/m-p/1209156#M167485" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/How-to-compute-S-CLKSETTLECTL-value-for-MIPI-CSI-2-receiver-on-i/m-p/1209156#M167485&lt;/A&gt;&lt;/DIV&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 29 Mar 2021 07:50:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1253418#M171670</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2021-03-29T07:50:46Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1256213#M172012</link>
      <description>&lt;P&gt;I set HS settle to 19 as I am using 448Mhz MIPI clock (measured using scope). One of the comments explained that the table is for DDR so I need the HS Settle value for 896Mhz which is 19.&lt;/P&gt;&lt;P&gt;Still I am unable to capture the 4-lane data.&lt;/P&gt;&lt;P&gt;Please correct me if my understanding is incorrect.&lt;/P&gt;</description>
      <pubDate>Fri, 02 Apr 2021 08:11:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1256213#M172012</guid>
      <dc:creator>namanthaker</dc:creator>
      <dc:date>2021-04-02T08:11:12Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1256655#M172069</link>
      <description>&lt;DIV&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/39586"&gt;@joanxie&lt;/a&gt;,&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Could you share below information about the 4-lane validation on i.MX8M Mini:&lt;/DIV&gt;&lt;DIV&gt;1. What was the sensor used for testing? As I understand, OV5640 supports up to 2-lane only.&lt;/DIV&gt;&lt;DIV&gt;2. Was the 4-lane data validated by observing the signals using scope on MIPI data lanes? If yes, could you share the images of the signals for reference if possible?&lt;/DIV&gt;3. Could you share the complete DTS file used by the development team for validating 4-lane?&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;DIV&gt;&lt;SPAN&gt;Naman Thaker&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Mon, 05 Apr 2021 10:38:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1256655#M172069</guid>
      <dc:creator>namanthaker</dc:creator>
      <dc:date>2021-04-05T10:38:09Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259610#M172346</link>
      <description>&lt;P&gt;sorry for missing this message, could you tell me what resolution and frame rate do you use? and any improvement about this? 19 should correct according to the table of hssettle settings, do you mind sending me your whole dts file and what's your resolution and frame rate?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 09 Apr 2021 10:25:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259610#M172346</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2021-04-09T10:25:08Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259613#M172347</link>
      <description>&lt;P&gt;I have sent to you a reference dts file for 4lane, pls check it&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 09 Apr 2021 10:34:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259613#M172347</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2021-04-09T10:34:22Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259639#M172351</link>
      <description>&lt;P&gt;I am using 2592x1944@30Hz i.e. 5MP@30hz resolution and framerate.&lt;/P&gt;&lt;P&gt;There was no improvement by setting hssettle value to 19.&lt;/P&gt;&lt;P&gt;Attached complete DTS for reference.&lt;/P&gt;</description>
      <pubDate>Fri, 09 Apr 2021 11:11:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259639#M172351</guid>
      <dc:creator>namanthaker</dc:creator>
      <dc:date>2021-04-09T11:11:46Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259646#M172354</link>
      <description>&lt;P&gt;I have not yet received the DTS file. Could you please share it again? Also, please let me know how you have sent the file.&lt;/P&gt;</description>
      <pubDate>Fri, 09 Apr 2021 11:33:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259646#M172354</guid>
      <dc:creator>namanthaker</dc:creator>
      <dc:date>2021-04-09T11:33:53Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259649#M172356</link>
      <description>&lt;P&gt;I have already sent to the DFAE, you should get the patch soon, this isn't official released version, I couldn't post here, and this patch is just for reference&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 09 Apr 2021 11:39:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259649#M172356</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2021-04-09T11:39:40Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259651#M172357</link>
      <description>&lt;P&gt;for 4-lane and 2-lane settings, did you compare their log file? anything different? did you get the correct log file when you set the 4-lane? and your dts file is limited, so you can refer to the patch first then tell me the result&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 09 Apr 2021 11:41:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259651#M172357</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2021-04-09T11:41:15Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259663#M172359</link>
      <description>&lt;P&gt;if you still failed with this, pls dump the mipi csi register, let me double check it, and send the log file (include 2-lane and 4-land,and confirm if you can get the correct data from the 4-lane on sensor side&lt;/P&gt;</description>
      <pubDate>Fri, 09 Apr 2021 12:08:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1259663#M172359</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2021-04-09T12:08:56Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with using MIPI-CSI 4-Lane on i.MX8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1261877#M172571</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/39586"&gt;@joanxie&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;Based on the patch I made a correction of adding "fsl,two-8bit-sensor-mode" property in the dts. Otherwise everything seems same. I still need to test with this property enabled.&lt;/P&gt;&lt;P&gt;My i.MX8MM + Camera setup needs some HW rework, as some of the wires are damaged. Getting them repaired will take me some time.&lt;BR /&gt;As soon as I have setup repaired I will test with the mentioned property and if it does not work I will capture the 2-lane and 4-lane logs and share them with you.&lt;/P&gt;&lt;P&gt;In the meantime could you please share me the steps to dump the mipi csi register?&lt;/P&gt;&lt;P&gt;Regards,&lt;BR /&gt;Naman&lt;/P&gt;</description>
      <pubDate>Wed, 14 Apr 2021 09:22:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-using-MIPI-CSI-4-Lane-on-i-MX8MM/m-p/1261877#M172571</guid>
      <dc:creator>namanthaker</dc:creator>
      <dc:date>2021-04-14T09:22:19Z</dc:date>
    </item>
  </channel>
</rss>

