https://community.nxp.com/t5/i-MX-Processors/failed-to-enable-l2-cache-on-imx6d/m-p/230527#M17228 <HTML><HEAD></HEAD><BODY><P>hello , i have ported sylixos(an rtos from china) to imx6d cpu which work at smp mode</P><P></P><P>i have a question, when i enable l2 cache, i write pl310 control register to 0x01, but i read it again, i found its value is 0x00, this mean i enable l2 cache failed,</P><P></P><P>why? </P></BODY></HTML> Sun, 12 Jan 2014 14:33:28 GMT jiaojinxing 2014-01-12T14:33:28Z https://community.nxp.com/t5/i-MX-Processors/failed-to-enable-l2-cache-on-imx6d/m-p/230527#M17228 <HTML><HEAD></HEAD><BODY><P>hello , i have ported sylixos(an rtos from china) to imx6d cpu which work at smp mode</P><P></P><P>i have a question, when i enable l2 cache, i write pl310 control register to 0x01, but i read it again, i found its value is 0x00, this mean i enable l2 cache failed,</P><P></P><P>why? </P></BODY></HTML> Sun, 12 Jan 2014 14:33:28 GMT https://community.nxp.com/t5/i-MX-Processors/failed-to-enable-l2-cache-on-imx6d/m-p/230527#M17228 jiaojinxing 2014-01-12T14:33:28Z https://community.nxp.com/t5/i-MX-Processors/failed-to-enable-l2-cache-on-imx6d/m-p/230528#M17229 <HTML><HEAD></HEAD><BODY><P>Hi, jinxing</P><P>&nbsp;&nbsp;&nbsp;&nbsp; Which register you wrote? The PL310's enable reg offset is 0x100, so you need to write 0x1 to 0xa02100.</P></BODY></HTML> Mon, 13 Jan 2014 06:45:33 GMT https://community.nxp.com/t5/i-MX-Processors/failed-to-enable-l2-cache-on-imx6d/m-p/230528#M17229 AnsonHuang 2014-01-13T06:45:33Z