i.MX ProcessorsのトピックRe: I.MX8MP support video format

I.MX8MP support video format

simonlin — Thu, 01 Apr 2021 11:06:03 GMT

I am trying to post Techpoint TV chip - TP2850 on I.MX8MP

I take ov5640 driver that in bsp for reference, because ov5640 work OK on I.MX8MP

Detect TP2850 chip and link device node successfully

[ 5.053390] TP2850 driver version 0.0.1 loaded
[ 5.062577] Detected TP2850
[ 5.128018] TP2850 Driver Init Successful!
[ 8.082111] mx8-img-md: Registered mxc_isi.0.capture as /dev/video0
[ 8.107778] mxc_isi_subdev_registered
[ 8.115642] mxc_isi_register_cap_device
[ 8.124309] mx8-img-md: Registered mxc_isi.1.capture as /dev/video1
[ 8.128009] hub 1-1:1.0: 4 ports detected
[ 8.165077] mx8-img-md: Registered sensor subdevice: tp2850_mipi 2-0044 (1)
[ 8.189878] mx8-img-md: created link [mxc_isi.0] => [mxc_isi.0.capture]
[ 8.206924] mx8-img-md: created link [mxc-mipi-csi2.0] => [mxc_isi.0]
[ 8.223783] mx8-img-md: created link [mxc_isi.1] => [mxc_isi.1.capture]
[ 8.237410] mx8-img-md: created link [tp2850_mipi 2-0044] => [mxc-mipi-csi2.0]

Use mx8_v4l2_cap_drm to recode file and save in USB storage, command as below
mx8_v4l2_cap_drm -cam 1 -d "/dev/video0" -fmt YUYV -ow 1920 -oh 1080 -of

There is no streaming output, soI dump the ISI and CSIS register

[ 62.662266] ISI CHNLC register dump, isi0
[ 62.666315] CHNL_CTRL[0x00]: e0000000
[ 62.670986] CHNL_IMG_CTRL[0x04]: 20000001
[ 62.675628] CHNL_OUT_BUF_CTRL[0x08]: 7c707
[ 62.680002] CHNL_IMG_CFG[0x0c]: 4380780
[ 62.684557] CHNL_IER[0x10]: 3cfc0000
[ 62.689194] CHNL_STS[0x14]: 100
[ 62.693397] CHNL_SCALE_FACTOR[0x18]: 10001000
[ 62.698034] CHNL_SCALE_OFFSET[0x1c]: 00
[ 62.702147] CHNL_CROP_ULC[0x20]: 00
[ 62.706263] CHNL_CROP_LRC[0x24]: 00
[ 62.710385] CHNL_CSC_COEFF0[0x28]: 00
[ 62.714507] CHNL_CSC_COEFF1[0x2c]: 00
[ 62.718625] CHNL_CSC_COEFF2[0x30]: 00
[ 62.722744] CHNL_CSC_COEFF3[0x34]: 00
[ 62.726863] CHNL_CSC_COEFF4[0x38]: 00
[ 62.730982] CHNL_CSC_COEFF5[0x3c]: 00
[ 62.735099] CHNL_ROI_0_ALPHA[0x40]: 00
[ 62.739219] CHNL_ROI_0_ULC[0x44]: 00
[ 62.743337] CHNL_ROI_0_LRC[0x48]: 00
[ 62.747457] CHNL_ROI_1_ALPHA[0x4c]: 00
[ 62.751571] CHNL_ROI_1_ULC[0x50]: 00
[ 62.758534] CHNL_ROI_1_LRC[0x54]: 00
[ 62.762646] CHNL_ROI_2_ALPHA[0x58]: 00
[ 62.766792] CHNL_ROI_2_ULC[0x5c]: 00
[ 62.770912] CHNL_ROI_2_LRC[0x60]: 00
[ 62.775046] CHNL_ROI_3_ALPHA[0x64]: 00
[ 62.779161] CHNL_ROI_3_ULC[0x68]: 00
[ 62.783275] CHNL_ROI_3_LRC[0x6c]: 00
[ 62.787391] CHNL_OUT_BUF1_ADDR_Y[0x70]: 76f00000
[ 62.792031] CHNL_OUT_BUF1_ADDR_U[0x74]: 00
[ 62.796142] CHNL_OUT_BUF1_ADDR_V[0x78]: 00
[ 62.800256] CHNL_OUT_BUF_PITCH[0x7c]: f00
[ 62.804458] CHNL_IN_BUF_ADDR[0x80]: 00
[ 62.808578] CHNL_IN_BUF_PITCH[0x84]: 00
[ 62.812695] CHNL_MEM_RD_CTRL[0x88]: 00
[ 62.816815] CHNL_OUT_BUF2_ADDR_Y[0x8c]: 73100000
[ 62.821453] CHNL_OUT_BUF2_ADDR_U[0x90]: 00
[ 62.825571] CHNL_OUT_BUF2_ADDR_V[0x94]: 00
[ 62.829688] CHNL_SCL_IMG_CFG[0x98]: 4380780
[ 62.834241] CHNL_FLOW_CTRL[0x9c]: 00

[ 79.255668] CSIS_VERSION[0]: 0x03060301
[ 79.260223] CSIS_CMN_CTRL[4]: 0x00004105
[ 79.267611] CSIS_CLK_CTRL[8]: 0x000f0000
[ 79.267613] CSIS_INTMSK[10]: 0x0fffff1f
[ 79.267615] CSIS_INTSRC[14]: 0x00000000
[ 79.267619] CSIS_DPHYSTATUS[20]: 0x000000c1
[ 79.267621] CSIS_DPHYCTRL[24]: 0x0d800007
[ 79.267624] CSIS_DPHYBCTRL_L[30]: 0x000001f4
[ 79.267626] CSIS_DPHYBCTRL_H[34]: 0x00000000
[ 79.267630] CSIS_DPHYSCTRL_L[38]: 0x00000000
[ 79.307095] CSIS_DPHYSCTRL_H[3c]: 0x00000000
[ 79.311736] CSIS_ISPCONFIG_CH0[40]: 0x00001078
[ 79.316362] CSIS_ISPCONFIG_CH1[50]: 0x000008fd
[ 79.320989] CSIS_ISPCONFIG_CH2[60]: 0x000008fe
[ 79.325613] CSIS_ISPCONFIG_CH3[70]: 0x000008ff
[ 79.330241] CSIS_ISPRESOL_CH0[44]: 0x04380780
[ 79.334865] CSIS_ISPRESOL_CH1[54]: 0x80008000
[ 79.339493] CSIS_ISPRESOL_CH2[64]: 0x80008000
[ 79.344117] CSIS_ISPRESOL_CH3[74]: 0x80008000
[ 79.348746] CSIS_ISPSYNC_CH0[48]: 0x00000000
[ 79.353368] CSIS_ISPSYNC_CH1[58]: 0x00000000
[ 79.357997] CSIS_ISPSYNC_CH2[68]: 0x00000000
[ 79.362623] CSIS_ISPSYNC_CH3[78]: 0x00000000
[ 79.367251] --- mipi_csis_s_stream ---
[ 79.371006] GPR_GASKET_0_CTRL[60]: 0x00001e02
[ 79.375632] GPR_GASKET_0_HSIZE[64]: 0x00001e02
[ 79.380258] GPR_GASKET_0_VSIZE[68]: 0x00001e02

I found CSIS_DPHYSTATUS[20]: 0x000000c1, it means Clock lane is in Stop State
My vendor FAE said the output format is different bewteen OV5640 and TP2850, as below photo

And TP2850 support virtual channel ID, imx8mp doesn't support it

OV5640

TP2850

Please give me some suggestion

Thanks

Re: I.MX8MP support video format

simonlin — Tue, 06 Apr 2021 01:18:42 GMT

Hi @igorpadykov

I found your article about imx8mp doesn't support MIPI-CSI virtual channels

Do you have any idea about my question?

Thanks

Re: I.MX8MP support video format

Zhiming_Liu — Tue, 06 Apr 2021 02:13:08 GMT

Hi simonlin

I found the CSIS IP Support interleave mode using Virtual channel.The clock and data lane2&3 are in stop state.

Zhiming

Re: I.MX8MP support video format

simonlin — Tue, 06 Apr 2021 02:36:43 GMT

Hi @Zhiming_Liu

I use 2 lanes (lane0、lane1) in this case, so the clock and data lane2&3 are in stop state is OK

About interleave mode, here is ov5640 register value for reference

The interleave mode setting of ov5640 and tp2850 is same

I found CHNL_CTRL[CSI_EN] is different between ov5640 and tp2850

How should I enable CHNL_CTRL[CSI_EN] ?

Thanks

[ 45.364412] ISI CHNLC register dump, isi1
[ 45.368434] CHNL_CTRL[0x00]: e0000001
[ 45.373067] CHNL_IMG_CTRL[0x04]: 20000001
[ 45.377699] CHNL_OUT_BUF_CTRL[0x08]: 7c707
[ 45.382068] CHNL_IMG_CFG[0x0c]: 1e002d0
[ 45.386611] CHNL_IER[0x10]: 3cfc0000
[ 45.391243] CHNL_STS[0x14]: 100
[ 45.395444] CHNL_SCALE_FACTOR[0x18]: 10001000
[ 45.400077] CHNL_SCALE_OFFSET[0x1c]: 00
[ 45.404185] CHNL_CROP_ULC[0x20]: 00
[ 45.408297] CHNL_CROP_LRC[0x24]: 00
[ 45.412411] CHNL_CSC_COEFF0[0x28]: 00
[ 45.416535] CHNL_CSC_COEFF1[0x2c]: 00
[ 45.420657] CHNL_CSC_COEFF2[0x30]: 00
[ 45.424769] CHNL_CSC_COEFF3[0x34]: 00
[ 45.428885] CHNL_CSC_COEFF4[0x38]: 00
[ 45.432997] CHNL_CSC_COEFF5[0x3c]: 00
[ 45.437107] CHNL_ROI_0_ALPHA[0x40]: 00
[ 45.441219] CHNL_ROI_0_ULC[0x44]: 00
[ 45.445330] CHNL_ROI_0_LRC[0x48]: 00
[ 45.449443] CHNL_ROI_1_ALPHA[0x4c]: 00
[ 45.453558] CHNL_ROI_1_ULC[0x50]: 00
[ 45.457672] CHNL_ROI_1_LRC[0x54]: 00
[ 45.461783] CHNL_ROI_2_ALPHA[0x58]: 00
[ 45.465893] CHNL_ROI_2_ULC[0x5c]: 00
[ 45.470006] CHNL_ROI_2_LRC[0x60]: 00
[ 45.474117] CHNL_ROI_3_ALPHA[0x64]: 00
[ 45.478228] CHNL_ROI_3_ULC[0x68]: 00
[ 45.482339] CHNL_ROI_3_LRC[0x6c]: 00
[ 45.486450] CHNL_OUT_BUF1_ADDR_Y[0x70]: da500000
[ 45.491082] CHNL_OUT_BUF1_ADDR_U[0x74]: 00
[ 45.495189] CHNL_OUT_BUF1_ADDR_V[0x78]: 00
[ 45.499301] CHNL_OUT_BUF_PITCH[0x7c]: 5a0
[ 45.503509] CHNL_IN_BUF_ADDR[0x80]: 00
[ 45.507616] CHNL_IN_BUF_PITCH[0x84]: 00
[ 45.511726] CHNL_MEM_RD_CTRL[0x88]: 00
[ 45.515841] CHNL_OUT_BUF2_ADDR_Y[0x8c]: da200000
[ 45.520491] CHNL_OUT_BUF2_ADDR_U[0x90]: 00
[ 45.524602] CHNL_OUT_BUF2_ADDR_V[0x94]: 00
[ 45.528715] CHNL_SCL_IMG_CFG[0x98]: 1e002d0
[ 45.533265] CHNL_FLOW_CTRL[0x9c]: 00

[ 53.981266] CSIS_VERSION[0]: 0x03060301
[ 53.985824] CSIS_CMN_CTRL[4]: 0x00004905
[ 53.990374] CSIS_CLK_CTRL[8]: 0x000f0000
[ 53.994925] CSIS_INTMSK[10]: 0x0fffff1f
[ 53.999555] CSIS_INTSRC[14]: 0x00000000
[ 54.004189] CSIS_DPHYSTATUS[20]: 0x000000c0
[ 54.008820] CSIS_DPHYCTRL[24]: 0x0d800007
[ 54.013454] CSIS_DPHYBCTRL_L[30]: 0x000001f4
[ 54.018089] CSIS_DPHYBCTRL_H[34]: 0x00000000
[ 54.022727] CSIS_DPHYSCTRL_L[38]: 0x00000000
[ 54.027364] CSIS_DPHYSCTRL_H[3c]: 0x00000000
[ 54.032001] CSIS_ISPCONFIG_CH0[40]: 0x00001078
[ 54.036643] CSIS_ISPCONFIG_CH1[50]: 0x000008fd
[ 54.041276] CSIS_ISPCONFIG_CH2[60]: 0x000008fe
[ 54.045926] CSIS_ISPCONFIG_CH3[70]: 0x000008ff
[ 54.050562] CSIS_ISPRESOL_CH0[44]: 0x01e002d0
[ 54.055193] CSIS_ISPRESOL_CH1[54]: 0x80008000
[ 54.059827] CSIS_ISPRESOL_CH2[64]: 0x80008000
[ 54.064457] CSIS_ISPRESOL_CH3[74]: 0x80008000
[ 54.069091] CSIS_ISPSYNC_CH0[48]: 0x00000000
[ 54.073722] CSIS_ISPSYNC_CH1[58]: 0x00000000
[ 54.078351] CSIS_ISPSYNC_CH2[68]: 0x00000000
[ 54.082979] CSIS_ISPSYNC_CH3[78]: 0x00000000

Thanks

Re: I.MX8MP support video format

Zhiming_Liu — Tue, 06 Apr 2021 03:42:07 GMT

The register set is in /drivers/staging/media/imx/imx8-mipi-csi2.c

Re: I.MX8MP support video format

simonlin — Tue, 06 Apr 2021 05:15:53 GMT

Hi @Zhiming_Liu

I already execute the mipi_csis_system_enable fucntion
But read the register value, CSI_EN is still disable

Thanks

Re: I.MX8MP support video format

Zhiming_Liu — Tue, 06 Apr 2021 06:27:53 GMT

Sorry for the previous repl ,the CHNL_CTRL register is in imx8-isi-hw.c!

Re: I.MX8MP support video format

simonlin — Wed, 07 Apr 2021 06:19:04 GMT

Hi @Zhiming_Liu

I check CHNL_CTRL register, and make sure it is OK for tp2850 and ov5640

Because tp2850 work on isi0, and ov5640 work on isi1

I found below ov5640 dts setting, it looks important about DPHY clock

How should I set csis-hs-settle and csis-clk-settle for tp2850?

mipi_csi0_ep: endpoint {
remote-endpoint = <&ov5640_mipi_0_ep>;
data-lanes = <2>;
csis-hs-settle = <13>;
csis-clk-settle = <2>;
csis-wclk;
};

Thanks

Re: I.MX8MP support video format

Zhiming_Liu — Thu, 08 Apr 2021 01:43:45 GMT

If the FAE can provide you the DIPD_HSI_MIPI_CSI-2_V3.6.3.1_User_Guide.pdf?

Re: I.MX8MP support video format

Zhiming_Liu — Thu, 08 Apr 2021 02:04:29 GMT

(FREQ. OF RX_BYTE_CLK_HS) X (NUMBER OF DATA LANE) X 8BITS
≤ (FREQ. OF PIXEL CLOCK) X (BITWIDTH OF IMAGE FORMAT) X (NUMBER OF PIXEL PER CLOCK)

The two params , you can see iMX_8M_Plus_RM_RevD.pdf,search the hssettle