i.MX ProcessorsのトピックLPDDR4 Data Channel Mapping with IMX8QM Data Channel Mapping https://community.nxp.com/t5/i-MX-Processors/LPDDR4-Data-Channel-Mapping-with-IMX8QM-Data-Channel-Mapping/m-p/1256680#M172071 <P><SPAN>Dear NXP,</SPAN></P><P>&nbsp;</P><P><SPAN>I doing channel mapping with <STRONG>BoardDataBusConfig</STRONG> section of <STRONG>MX8QM_B0_LPDDR4_RPA_1.6GHz_v17.xlsx</STRONG> after this configuration some of the value is not mapping properly.</SPAN><BR /><BR /><STRONG>PHY0</STRONG><BR /><BR /><SPAN>DATA 4 DDR_PHY_DX2DQMAP0_0 <STRONG>#N/A</STRONG> // DQ bit 0/1/2/3/4 remapping</SPAN><BR /><SPAN>DATA 4 DDR_PHY_DX2DQMAP1_0 <STRONG>#N/A</STRONG> // DQ bit 5/6/7 and DM remapping</SPAN><BR /><SPAN>DATA 4 DDR_PHY_DX3DQMAP0_0 <STRONG>#N/A</STRONG> // DQ bit 0/1/2/3/4 remapping</SPAN><BR /><SPAN>DATA 4 DDR_PHY_DX3DQMAP1_0 <STRONG>#N/A</STRONG> // DQ bit 5/6/7 and DM remapping</SPAN><BR /><BR /><BR /><STRONG>PHY1</STRONG><BR /><BR /><SPAN>DATA 4 DDR_PHY_DX2DQMAP0_1 <STRONG>#N/A</STRONG> // DQ bit 0/1/2/3/4 remapping</SPAN><BR /><SPAN>DATA 4 DDR_PHY_DX2DQMAP1_1 <STRONG>#N/A</STRONG> // DQ bit 5/6/7 and DM remapping</SPAN><BR /><SPAN>DATA 4 DDR_PHY_DX3DQMAP0_1 <STRONG>#N/A</STRONG> // DQ bit 0/1/2/3/4 remapping</SPAN><BR /><SPAN>DATA 4 DDR_PHY_DX3DQMAP1_1 <STRONG>#N/A</STRONG> // DQ bit 5/6/7 and DM remapping</SPAN></P><P>&nbsp;</P> Mon, 05 Apr 2021 12:48:44 GMT vinothkumars 2021-04-05T12:48:44Z LPDDR4 Data Channel Mapping with IMX8QM Data Channel Mapping https://community.nxp.com/t5/i-MX-Processors/LPDDR4-Data-Channel-Mapping-with-IMX8QM-Data-Channel-Mapping/m-p/1256680#M172071 <P><SPAN>Dear NXP,</SPAN></P><P>&nbsp;</P><P><SPAN>I doing channel mapping with <STRONG>BoardDataBusConfig</STRONG> section of <STRONG>MX8QM_B0_LPDDR4_RPA_1.6GHz_v17.xlsx</STRONG> after this configuration some of the value is not mapping properly.</SPAN><BR /><BR /><STRONG>PHY0</STRONG><BR /><BR /><SPAN>DATA 4 DDR_PHY_DX2DQMAP0_0 <STRONG>#N/A</STRONG> // DQ bit 0/1/2/3/4 remapping</SPAN><BR /><SPAN>DATA 4 DDR_PHY_DX2DQMAP1_0 <STRONG>#N/A</STRONG> // DQ bit 5/6/7 and DM remapping</SPAN><BR /><SPAN>DATA 4 DDR_PHY_DX3DQMAP0_0 <STRONG>#N/A</STRONG> // DQ bit 0/1/2/3/4 remapping</SPAN><BR /><SPAN>DATA 4 DDR_PHY_DX3DQMAP1_0 <STRONG>#N/A</STRONG> // DQ bit 5/6/7 and DM remapping</SPAN><BR /><BR /><BR /><STRONG>PHY1</STRONG><BR /><BR /><SPAN>DATA 4 DDR_PHY_DX2DQMAP0_1 <STRONG>#N/A</STRONG> // DQ bit 0/1/2/3/4 remapping</SPAN><BR /><SPAN>DATA 4 DDR_PHY_DX2DQMAP1_1 <STRONG>#N/A</STRONG> // DQ bit 5/6/7 and DM remapping</SPAN><BR /><SPAN>DATA 4 DDR_PHY_DX3DQMAP0_1 <STRONG>#N/A</STRONG> // DQ bit 0/1/2/3/4 remapping</SPAN><BR /><SPAN>DATA 4 DDR_PHY_DX3DQMAP1_1 <STRONG>#N/A</STRONG> // DQ bit 5/6/7 and DM remapping</SPAN></P><P>&nbsp;</P> Mon, 05 Apr 2021 12:48:44 GMT https://community.nxp.com/t5/i-MX-Processors/LPDDR4-Data-Channel-Mapping-with-IMX8QM-Data-Channel-Mapping/m-p/1256680#M172071 vinothkumars 2021-04-05T12:48:44Z