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    <title>i.MX ProcessorsのトピックRe: iMX7 Relocating M4 Code to DDR</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1255948#M171981</link>
    <description>&lt;P&gt;Hi Igor&lt;/P&gt;&lt;P&gt;Thanks for your response. The AN talks about OCR and TCM and loading a new image at run time. Unfortunately it still does not help me understand the following:&lt;/P&gt;&lt;P&gt;My M4 code is currently running from TCM. I will modify my M4 code to run from DDR. Do I also need to rebuild my make change to my Yocto Linux image or will it work without a change to the Linux image?&lt;/P&gt;&lt;P&gt;Thanks in advance&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 01 Apr 2021 18:46:04 GMT</pubDate>
    <dc:creator>Duracell</dc:creator>
    <dc:date>2021-04-01T18:46:04Z</dc:date>
    <item>
      <title>iMX7 Relocating M4 Code to DDR</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1253618#M171705</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;I currently have a board with iMX7d. The M4 is running from TCM. I already have units in field but I am not able to remotely update uBoot.&amp;nbsp;I can update Linux remotely.&lt;/P&gt;&lt;P&gt;I now want to run the M4 code from DDR. Can this be done with only changing the Linux image and not changing uBoot?&lt;/P&gt;&lt;P&gt;Thanks in advance&lt;/P&gt;</description>
      <pubDate>Mon, 29 Mar 2021 12:58:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1253618#M171705</guid>
      <dc:creator>Duracell</dc:creator>
      <dc:date>2021-03-29T12:58:56Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7 Relocating M4 Code to DDR</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1253854#M171739</link>
      <description>&lt;P&gt;Hi Sean&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;one can try procedures described in below documents&lt;/P&gt;
&lt;P&gt;AN5317&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;A id="relatedDocsClick_3" href="https://www.nxp.com/docs/en/application-note/AN5317.pdf" target="_blank" rel="noopener"&gt;&lt;STRONG&gt;Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors&lt;/STRONG&gt;&lt;/A&gt;&lt;BR /&gt;&lt;A href="https://github.com/NXPmicro/imx-m4fwloader" target="_blank" rel="noopener"&gt;https://github.com/NXPmicro/imx-m4fwloader&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;</description>
      <pubDate>Tue, 30 Mar 2021 00:54:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1253854#M171739</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2021-03-30T00:54:04Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7 Relocating M4 Code to DDR</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1255948#M171981</link>
      <description>&lt;P&gt;Hi Igor&lt;/P&gt;&lt;P&gt;Thanks for your response. The AN talks about OCR and TCM and loading a new image at run time. Unfortunately it still does not help me understand the following:&lt;/P&gt;&lt;P&gt;My M4 code is currently running from TCM. I will modify my M4 code to run from DDR. Do I also need to rebuild my make change to my Yocto Linux image or will it work without a change to the Linux image?&lt;/P&gt;&lt;P&gt;Thanks in advance&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 01 Apr 2021 18:46:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1255948#M171981</guid>
      <dc:creator>Duracell</dc:creator>
      <dc:date>2021-04-01T18:46:04Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7 Relocating M4 Code to DDR</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1255949#M171982</link>
      <description>&lt;P&gt;eg. does the Linux memory map need to be adjusted and Linux therefore needs to be rebuilt?&lt;/P&gt;</description>
      <pubDate>Thu, 01 Apr 2021 18:54:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1255949#M171982</guid>
      <dc:creator>Duracell</dc:creator>
      <dc:date>2021-04-01T18:54:20Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7 Relocating M4 Code to DDR</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1255952#M171983</link>
      <description>&lt;P&gt;also, does uBoot need to be recompiled to accommodate this change?&lt;/P&gt;</description>
      <pubDate>Thu, 01 Apr 2021 18:59:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1255952#M171983</guid>
      <dc:creator>Duracell</dc:creator>
      <dc:date>2021-04-01T18:59:05Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7 Relocating M4 Code to DDR</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1256018#M171988</link>
      <description>&lt;P&gt;may be useful to look at below link&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Kernel-when-relocated-outside-of-first-2MB-of-RAM/m-p/685575" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/Kernel-when-relocated-outside-of-first-2MB-of-RAM/m-p/685575&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 02 Apr 2021 00:33:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1256018#M171988</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2021-04-02T00:33:50Z</dc:date>
    </item>
    <item>
      <title>Re: iMX7 Relocating M4 Code to DDR</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1256210#M172011</link>
      <description>&lt;P&gt;It is&amp;nbsp; related to M4. Please search&amp;nbsp;i.MX6SX_M4_MPU_Settings_For_RPMSG_08102018.pdf in the below link.&lt;/P&gt;
&lt;P&gt;Although it is i.MX6SX, it is the same knowledge.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;i.MX Development Miscellanea(i.MX 开发杂记)&lt;BR /&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-Development-Miscellanea-i-MX-%E5%BC%80%E5%8F%91%E6%9D%82%E8%AE%B0/ta-p/1104265" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-Development-Miscellanea-i-MX-%E5%BC%80%E5%8F%91%E6%9D%82%E8%AE%B0/ta-p/1104265&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 02 Apr 2021 08:09:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX7-Relocating-M4-Code-to-DDR/m-p/1256210#M172011</guid>
      <dc:creator>BiyongSUN</dc:creator>
      <dc:date>2021-04-02T08:09:06Z</dc:date>
    </item>
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