topic Re: About imx8mp hdmi clock documentation in i.MX Processors

About imx8mp hdmi clock documentation

Chun1 — Mon, 29 Mar 2021 08:52:50 GMT

When I write the hdmi clock of imx8mp, I found that the bit used by Linux does not match the documentation. The bits is called 'hdmi_fdcc_ref' in Linux, and it use the second bit of register HDMI_RTX_CLK_CTL1(0x50). But the bit described in the document is reserved. Is my document not up-to-date? Or is it for some other reason? The document I use is iMX_8M_Plus_RM_RevD.pdf. Thanks.

Re: About imx8mp hdmi clock documentation

joanxie — Wed, 31 Mar 2021 06:38:13 GMT

D version is the latest version, could you send the source path you mention 'hdmi_fdcc_ref' in Linux

Re: About imx8mp hdmi clock documentation

Chun1 — Wed, 31 Mar 2021 11:58:13 GMT

I clone the code from link:https://source.codeaurora.org/external/imx/linux-imx

and checkout to the branch: imx_5.4.70_2.3.0

the code is in `imx_hdmimix_clk_probe` function of the file `drivers/clk/imx/clk-hdmimix.c`.

clks[IMX8MP_CLK_HDMIMIX_FDCC_REF_CLK] = imx_dev_clk_gate(dev, "hdmi_fdcc_ref", "hdmi_fdcc_tst", base + 0x50, 2); clks[IMX8MP_CLK_HDMIMIX_HRV_MWR_APB_CLK] = imx_dev_clk_gate(dev, "hrv_mwr_apb", "hdmi_glb_apb", base + 0x50, 3);

Re: About imx8mp hdmi clock documentation

joanxie — Thu, 01 Apr 2021 09:18:15 GMT

thanks for your information, I checked the hdmi IP,

FDCC_REF_CLK_EN: FDCC_REF_CLK_EN control
clock enable for the ref_clk input of FDCC

you can refer to this

Re: About imx8mp hdmi clock documentation

Chun1 — Thu, 01 Apr 2021 10:16:35 GMT

'''

FDCC_REF_CLK_EN: FDCC_REF_CLK_EN control
clock enable for the ref_clk input of FDCC

'''

You mean this is the description of bit2 of HDMI_RTX_CLK_CTL1(0x50)， not the reserved value?

Re: About imx8mp hdmi clock documentation

joanxie — Fri, 02 Apr 2021 07:36:13 GMT

I just copy the content from IP spec, you just set the same as our bsp does