topic i.MX8M Nano Cortex-M7 code execution on DDR memory in i.MX Processors

i.MX8M Nano Cortex-M7 code execution on DDR memory

timada — Wed, 31 Mar 2021 05:58:08 GMT

Hi,

Could you please tell me the specification of DDR memory access policy for i.MX8M Nano Cortex-M7?

I have tried to run a i.MX8M Nano Cortex-M7 program located at a DDR memory region, but the program could not execute when it was located at 0x40000000 - 0x5FFFFFFF.
Program execution was successful if the program was located at 0x60000000 or higher.

On the other hand, Read/Write access to/from 0x40000000 - 0x5FFFFFFF by Cortex-M7 was successful.
(Read/Write access from/to 0x60000000 or higher by Cortex-M7 was successful too)

I've also checked a stored value of Memory Region Control (RDC_MRCn), but it indicated that no memory access policy was enforced.

A web site[1] describes a similar problem, but it does not have any useful information on this issue.

(Test configuration)
Board: 8MNANOD4-EVK
Boot : TF-A and u-boot from L5.4.70_2.3.0_MX8MN

[1] http://variwiki.com/index.php?title=MCUXpresso&release=MCUXPRESSO_2.7.0_V1.0_VAR-SOM-MX8M-NANO#Memory_types

Re: i.MX8M Nano Cortex-M7 code execution on DDR memory

AldoG — Wed, 31 Mar 2021 20:20:49 GMT

Hello,

The Arm cortex M7 processor behavior of memory access, address from 0x40000000 to 0x5FFFFFFF is used for peripheral address space and is execute never region.

Best regards,
Aldo.

Re: i.MX8M Nano Cortex-M7 code execution on DDR memory

timada — Thu, 01 Apr 2021 01:41:08 GMT

Do you mean that the memory region 0x40000000 - 0x5FFFFFFF is not mapped to DDR SDRAM?
Otherwise, is it mapped to DDR SDRAM with the "execution prohibited" policy?

I would like to understand detailed memory map information for the whole region of DDR SDRAM (0x40000000 - 0xBFFFFFFF from the latest reference manual) for Cortex-M7.

Could you please provide me with a simple table below for the region 0x40000000 - 0xBFFFFFFF?

Start address	End address	Mapped device	Access policy
0x40000000	0x5FFFFFFF	DDR?	Execution prohibited
0x60000000	...	...	...
...	...	...	...

Many thanks,

Re: i.MX8M Nano Cortex-M7 code execution on DDR memory

AldoG — Thu, 08 Apr 2021 19:42:53 GMT

Hello,

For this you may refer to the ARM Cortex-M7 user guide

https://developer.arm.com/documentation/dui0646/a/the-cortex-m7-processor/memory-model/behavior-of-memory-accesses

Best regards,
Aldo.

Re: i.MX8M Nano Cortex-M7 code execution on DDR memory

timada — Tue, 13 Apr 2021 07:23:14 GMT

Could you please tell me if or not the Cortex-M7 memory access policy is applied to i.MX8M Plus too?

Many thanks,