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  <channel>
    <title>i.MX ProcessorsのトピックRe: Enabling CoreSight on i.MX 8MM</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1250225#M171265</link>
    <description>&lt;P&gt;You should change like:&lt;/P&gt;
&lt;PRE&gt;status = "okay";&lt;/PRE&gt;</description>
    <pubDate>Tue, 23 Mar 2021 08:08:54 GMT</pubDate>
    <dc:creator>Zhiming_Liu</dc:creator>
    <dc:date>2021-03-23T08:08:54Z</dc:date>
    <item>
      <title>Enabling CoreSight on i.MX 8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1243084#M170613</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; We're using Yocto Zeus and would like to embed CoreSight for hardware assisted tracing. We enable this by integrating opencsd to the perf tool, but the source and sink drivers are missing.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; We verified that the kernel is configured correctly to include the CoreSight modules but the device tree is lacking the hw trace addresses for etm.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; So we request you to provide the &lt;STRONG&gt;etm address for the A53 core&lt;/STRONG&gt;s and the related data. It would be helpful if you could share the example Device tree with coresight enabled.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; Another question is that how can we include coresight into the perf tool? As the included perf recipe is missing the coresight package configuration.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;</description>
      <pubDate>Wed, 10 Mar 2021 08:08:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1243084#M170613</guid>
      <dc:creator>kanimozhi_t</dc:creator>
      <dc:date>2021-03-10T08:08:54Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling CoreSight on i.MX 8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1243799#M170657</link>
      <description>&lt;P&gt;I have asked the expert and will update later&lt;/P&gt;</description>
      <pubDate>Thu, 11 Mar 2021 02:52:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1243799#M170657</guid>
      <dc:creator>Zhiming_Liu</dc:creator>
      <dc:date>2021-03-11T02:52:14Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling CoreSight on i.MX 8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1244483#M170736</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Since 8MM shares same cores' design as 8MP, you can take reference of how to define ETM and related coresight nodes on 8MP:&amp;nbsp;arch/arm64/boot/dts/freescale/imx8mp.dtsi. The coresight driver in kernel is create PMU events for perf, so after you enabled coresight driver, perf can see it:&amp;nbsp;&lt;/SPAN&gt;&lt;A href="https://www.kernel.org/doc/Documentation/trace/coresight.txt" target="_blank" rel="nofollow noopener noreferrer"&gt;https://www.kernel.org/doc/Documentation/trace/coresight.txt&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 12 Mar 2021 01:46:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1244483#M170736</guid>
      <dc:creator>Zhiming_Liu</dc:creator>
      <dc:date>2021-03-12T01:46:50Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling CoreSight on i.MX 8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1244785#M170781</link>
      <description>&lt;P&gt;Thanks&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/151788"&gt;@Zhiming_Liu&lt;/a&gt;&amp;nbsp;for your valuable information.&lt;/P&gt;&lt;P&gt;I've added the following lines from &lt;STRONG&gt;im8mp.dtsi&lt;/STRONG&gt; (with modified clocks, &lt;I&gt;IMX8MP_CLK_MAIN_AXI -&amp;gt; IMX8MQ_CLK_MAIN_AXI&lt;/I&gt;)&lt;/P&gt;&lt;PRE&gt;etm0: etm@28440000 {
    compatible = "arm,coresight-etm4x", "arm,primecell";
    reg = &amp;lt;0x0 0x28440000 0x0 0x10000&amp;gt;;
    arm,primecell-periphid = &amp;lt;0xbb95d&amp;gt;;
    cpu = &amp;lt;&amp;amp;A53_0&amp;gt;;
    clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_MAIN_AXI&amp;gt;;
    clock-names = "apb_pclk";
    status = "disabled";

        out-ports {
            port {
            etm0_out_port: endpoint {
                remote-endpoint = &amp;lt;&amp;amp;ca_funnel_in_port0&amp;gt;;
            };
        };
    };
};

etm1: etm@28540000 {
    compatible = "arm,coresight-etm4x", "arm,primecell";
    reg = &amp;lt;0x0 0x28540000 0x0 0x10000&amp;gt;;
    arm,primecell-periphid = &amp;lt;0xbb95d&amp;gt;;
    cpu = &amp;lt;&amp;amp;A53_1&amp;gt;;
    clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_MAIN_AXI&amp;gt;;
    clock-names = "apb_pclk";
    status = "disabled";

    out-ports {
        port {
            etm1_out_port: endpoint {
                remote-endpoint = &amp;lt;&amp;amp;ca_funnel_in_port1&amp;gt;;
            };
        };
    };
};

etm2: etm@28640000 {
    compatible = "arm,coresight-etm4x", "arm,primecell";
    reg = &amp;lt;0x0 0x28640000 0x0 0x10000&amp;gt;;
    arm,primecell-periphid = &amp;lt;0xbb95d&amp;gt;;
    cpu = &amp;lt;&amp;amp;A53_2&amp;gt;;
    clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_MAIN_AXI&amp;gt;;
    clock-names = "apb_pclk";
    status = "disabled";

    out-ports {
        port {
            etm2_out_port: endpoint {
                remote-endpoint = &amp;lt;&amp;amp;ca_funnel_in_port2&amp;gt;;
            };
        };
    };
};

etm3: etm@28740000 {
    compatible = "arm,coresight-etm4x", "arm,primecell";
    reg = &amp;lt;0x0 0x28740000 0x0 0x10000&amp;gt;;
    arm,primecell-periphid = &amp;lt;0xbb95d&amp;gt;;
    cpu = &amp;lt;&amp;amp;A53_3&amp;gt;;
    clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_MAIN_AXI&amp;gt;;
    clock-names = "apb_pclk";
    status = "disabled";

    out-ports {
        port {
            etm3_out_port: endpoint {
                remote-endpoint = &amp;lt;&amp;amp;ca_funnel_in_port3&amp;gt;;
            };
        };
    };
};

funnel0: funnel {
        /*
    * non-configurable funnel don't show up on the AMBA
    * bus.  As such no need to add "arm,primecell".
    */
    compatible = "arm,coresight-static-funnel";
    status = "disabled";

    in-ports {
        #address-cells = &amp;lt;1&amp;gt;;
        #size-cells = &amp;lt;0&amp;gt;;

        port@0 {
            reg = &amp;lt;0&amp;gt;;
            ca_funnel_in_port0: endpoint {
                remote-endpoint = &amp;lt;&amp;amp;etm0_out_port&amp;gt;;
            };
        };

        port@1 {
            reg = &amp;lt;1&amp;gt;;
            ca_funnel_in_port1: endpoint {
                remote-endpoint = &amp;lt;&amp;amp;etm1_out_port&amp;gt;;
            };
        };

        port@2 {
            reg = &amp;lt;2&amp;gt;;
            ca_funnel_in_port2: endpoint {
                remote-endpoint = &amp;lt;&amp;amp;etm2_out_port&amp;gt;;
            };
        };

        port@3 {
            reg = &amp;lt;3&amp;gt;;
            ca_funnel_in_port3: endpoint {
                remote-endpoint = &amp;lt;&amp;amp;etm3_out_port&amp;gt;;
            };
        };
    };

    out-ports {
        port {
            ca_funnel_out_port0: endpoint {
                remote-endpoint = &amp;lt;&amp;amp;hugo_funnel_in_port0&amp;gt;;
            };
        };
    };

};

funnel1: funnel@28c03000 {
    compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
    reg = &amp;lt;0x0 0x28c03000 0x0 0x1000&amp;gt;;
    clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_MAIN_AXI&amp;gt;;
    clock-names = "apb_pclk";
    status = "disabled";

    in-ports {
        #address-cells = &amp;lt;1&amp;gt;;
        #size-cells = &amp;lt;0&amp;gt;;

        port@0 {
            reg = &amp;lt;0&amp;gt;;
            hugo_funnel_in_port0: endpoint {
                remote-endpoint = &amp;lt;&amp;amp;ca_funnel_out_port0&amp;gt;;
            };
        };

        port@1 {
            reg = &amp;lt;1&amp;gt;;
            hugo_funnel_in_port1: endpoint {
                /* M7 input */
            };
        };

        port@2 {
            reg = &amp;lt;2&amp;gt;;
            hugo_funnel_in_port2: endpoint {
                /* DSP input */
            };
        };
        /* the other input ports are not connect to anything */
    };

    out-ports {
        port {
            hugo_funnel_out_port0: endpoint {
                remote-endpoint = &amp;lt;&amp;amp;etf_in_port&amp;gt;;
            };
        };
    };
};

etf@28c04000 {
    compatible = "arm,coresight-tmc", "arm,primecell";
    reg = &amp;lt;0x0 0x28c04000 0x0 0x1000&amp;gt;;
    clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_MAIN_AXI&amp;gt;;
    clock-names = "apb_pclk";
    status = "disabled";

    in-ports {
        port {
            etf_in_port: endpoint {
                remote-endpoint = &amp;lt;&amp;amp;hugo_funnel_out_port0&amp;gt;;
            };
        };
    };

    out-ports {
        port {
            etf_out_port: endpoint {
                remote-endpoint = &amp;lt;&amp;amp;etr_in_port&amp;gt;;
            };
        };
    };
};

etr@28c06000 {
    compatible = "arm,coresight-tmc", "arm,primecell";
    reg = &amp;lt;0x0 0x28c06000 0x0 0x1000&amp;gt;;
    clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_MAIN_AXI&amp;gt;;
    clock-names = "apb_pclk";
    status = "disabled";

    in-ports {
        port {
            etr_in_port: endpoint {
                remote-endpoint = &amp;lt;&amp;amp;etf_out_port&amp;gt;;
            };
        };
    };
};&lt;/PRE&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;However, the /sys/bus/coresight/devices/ are still empty:&lt;/DIV&gt;&lt;PRE&gt;root@imx8mq:/# ls -la /sys/bus/coresight/devices/
total 0
drwxr-xr-x 2 root root 0 Jan 13 10:46 .
drwxr-xr-x 4 root root 0 Jan 13 10:46 .. &lt;/PRE&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;But I got the &lt;STRONG&gt;ETM Modules,&lt;/STRONG&gt; listed as follows&lt;/DIV&gt;&lt;PRE&gt;root@imx8mq:/# find . -name "*etm*"
./usr/bin/setmetamode
./sys/devices/cs_etm
./sys/bus/amba/drivers/coresight-etm4x
./sys/bus/event_source/devices/cs_etm
./sys/firmware/devicetree/base/etm@28740000
./sys/firmware/devicetree/base/etm@28640000
./sys/firmware/devicetree/base/etm@28540000
./sys/firmware/devicetree/base/etm@28440000
./sys/module/coresight_etm4x&lt;/PRE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;DIV&gt;So, my questions are:&lt;/DIV&gt;&lt;H3&gt;1. How to make available of the CoreSight sinks and sources?&lt;/H3&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;H3&gt;2. How to check the perf tool for CoreSight integration?&lt;/H3&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;DIV&gt;Thanks in advance!&lt;/DIV&gt;</description>
      <pubDate>Fri, 12 Mar 2021 10:55:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1244785#M170781</guid>
      <dc:creator>kanimozhi_t</dc:creator>
      <dc:date>2021-03-12T10:55:26Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling CoreSight on i.MX 8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1249663#M171211</link>
      <description>&lt;P&gt;&lt;EM&gt;To add additional context&lt;/EM&gt;, I've taken the lines related to CoreSight (EMT, Funnel, etc.,) lines from the "&lt;FONT color="#0000FF"&gt;imx8mp.dtsi&lt;/FONT&gt;" file and paste the same in the "&lt;FONT color="#0000FF"&gt;imx8mq.dtsi&lt;/FONT&gt;" file.&lt;/P&gt;&lt;P&gt;During this process, I had to change the "I&lt;EM&gt;MX8MP_CLK_MAIN_AXI&lt;/EM&gt;" to "&lt;EM&gt;IMX8MQ_CLK_MAIN_AXI&lt;/EM&gt;" for mitigating the build errors. Apart from this change the &lt;FONT color="#008000"&gt;build succeeds without any further modifications&lt;/FONT&gt;.&lt;/P&gt;&lt;P&gt;But even after this addition in device tree, the Linux filesystem &lt;FONT color="#FF0000"&gt;does not include&lt;/FONT&gt; any of the &lt;FONT color="#FF0000"&gt;CoreSight devices&lt;/FONT&gt;.&lt;/P&gt;&lt;P&gt;So, it raises the following questions:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;FONT color="#0000FF"&gt;&lt;FONT color="#0000FF"&gt;&lt;STRONG&gt;Is the address of ETM for i.MX 8MP and i.MX 8MQ same? &lt;FONT color="#800080"&gt;Eg: for etm1&lt;/FONT&gt;&lt;/STRONG&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;PRE&gt;reg = &amp;lt;0x0 0x28440000 0x0 0x10000&amp;gt;;&lt;/PRE&gt;&lt;/LI&gt;&lt;LI&gt;&lt;FONT color="#0000FF"&gt;&lt;STRONG&gt;What is the purpose of the line &lt;FONT color="#800080"&gt;status = "disabled"&amp;nbsp;&lt;/FONT&gt;? Do I need to enable it?&lt;/STRONG&gt;&lt;/FONT&gt;&lt;/LI&gt;&lt;LI&gt;&lt;FONT color="#0000FF"&gt;&lt;STRONG&gt;Where can I find the ETM addresses for i.MX 8MQ?&lt;/STRONG&gt;&lt;/FONT&gt;&lt;/LI&gt;&lt;/OL&gt;</description>
      <pubDate>Mon, 22 Mar 2021 12:03:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1249663#M171211</guid>
      <dc:creator>kanimozhi_t</dc:creator>
      <dc:date>2021-03-22T12:03:11Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling CoreSight on i.MX 8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1249964#M171229</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;1.The ETM address of i.MX8M series is same.They are the same cpu ip.&lt;/P&gt;
&lt;P&gt;2.You must &lt;EM&gt;&lt;STRONG&gt;enable&lt;/STRONG&gt;&lt;/EM&gt; it if you wants to use node&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Zhiming&lt;/P&gt;</description>
      <pubDate>Tue, 23 Mar 2021 01:39:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1249964#M171229</guid>
      <dc:creator>Zhiming_Liu</dc:creator>
      <dc:date>2021-03-23T01:39:52Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling CoreSight on i.MX 8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1250201#M171263</link>
      <description>&lt;P&gt;Even after &lt;FONT color="#008000"&gt;enabling&lt;/FONT&gt; all the nodes in the above &lt;A href="https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1244785/highlight/true#M170781" target="_self"&gt;Device Tree fragment above&lt;/A&gt; as,&lt;/P&gt;&lt;PRE&gt;status = "enabled";&lt;/PRE&gt;&lt;P&gt;the CoreSight devices are &lt;STRONG&gt;empty&lt;/STRONG&gt; in the Linux.&lt;/P&gt;&lt;P&gt;&lt;FONT color="#0000FF"&gt;&lt;STRONG&gt;Do you have any idea of what would've gone wrong or further debugging steps?&lt;/STRONG&gt;&lt;/FONT&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 23 Mar 2021 07:42:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1250201#M171263</guid>
      <dc:creator>kanimozhi_t</dc:creator>
      <dc:date>2021-03-23T07:42:50Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling CoreSight on i.MX 8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1250225#M171265</link>
      <description>&lt;P&gt;You should change like:&lt;/P&gt;
&lt;PRE&gt;status = "okay";&lt;/PRE&gt;</description>
      <pubDate>Tue, 23 Mar 2021 08:08:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1250225#M171265</guid>
      <dc:creator>Zhiming_Liu</dc:creator>
      <dc:date>2021-03-23T08:08:54Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling CoreSight on i.MX 8MM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1250250#M171267</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/151788"&gt;@Zhiming_Liu&lt;/a&gt;&amp;nbsp;Thanks for your swift replies and helping us to get it worked.&lt;/P&gt;</description>
      <pubDate>Tue, 23 Mar 2021 08:45:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Enabling-CoreSight-on-i-MX-8MM/m-p/1250250#M171267</guid>
      <dc:creator>kanimozhi_t</dc:creator>
      <dc:date>2021-03-23T08:45:50Z</dc:date>
    </item>
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