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    <title>i.MX ProcessorsのトピックRe: IMX515 Fuze Bits</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX515-Fuze-Bits/m-p/230034#M17111</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Problem solved!&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="en"&gt;&lt;SPAN class="hps"&gt;The algorithm&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;above&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;is correct&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;but I&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;also&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;need to set the&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;bit:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;efuse_prog_supply_gate (CGPR -&amp;gt; 0x73FD_4064),&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="en"&gt;&lt;SPAN class="hps"&gt;(and&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;additional information&lt;/SPAN&gt;&lt;SPAN&gt;, you must&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;have a&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;3.3 V&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;on pin&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;VDD_FUSE).&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="en"&gt;&lt;SPAN class="hps"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="en"&gt;&lt;SPAN class="hps"&gt;Lukas.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 01 Aug 2013 09:47:50 GMT</pubDate>
    <dc:creator>wysockilukasz</dc:creator>
    <dc:date>2013-08-01T09:47:50Z</dc:date>
    <item>
      <title>IMX515 Fuze Bits</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX515-Fuze-Bits/m-p/230033#M17110</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have problem with IIC module for IM515. I'm traing to burn fuse bits using Lauterbach Jtag and&lt;/P&gt;&lt;P&gt;programing sequency from RM (page 1174).&lt;BR /&gt;For example for fuse FB0REG1 ADDR: 0x83f98844 (default value:0x00)&lt;/P&gt;&lt;P&gt;I would like to achieve value 0x60 (set BT_LPB_FREQ[2:0] = b011)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;To do that I'm wrote a short script in TRACE32:&lt;/P&gt;&lt;P&gt;//////////////////////first bit&lt;/P&gt;&lt;P&gt;//Write 8’hAA to PRG_P&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Data.Set d:83F98028 %l 0xAA&lt;/P&gt;&lt;P&gt;//User writes target bit address to UPA/LPA using IP Bus&lt;/P&gt;&lt;P&gt;//UA&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Data.Set d:83F98014 %l 0x00&lt;/P&gt;&lt;P&gt;//LA&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Data.Set d:83F98018 %l 0x8D&lt;/P&gt;&lt;P&gt;//User sets PRG bit&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Data.Set d:83F98010 %l 0x01&lt;/P&gt;&lt;P&gt;//Set PROGD in STAT&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Data.Set d:83F98000 %l 0x02&lt;/P&gt;&lt;P&gt;///////////////////////// second bit&lt;/P&gt;&lt;P&gt;//Write 8’hAA to PRG_P&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Data.Set d:83F98028 %l 0xAA&lt;/P&gt;&lt;P&gt;//User writes target bit address to UPA/LPA using IP Bus&lt;/P&gt;&lt;P&gt;//UA&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Data.Set d:83F98014 %l 0x00&lt;/P&gt;&lt;P&gt;//LA&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Data.Set d:83F98018 %l 0x8E&lt;/P&gt;&lt;P&gt;//User sets PRG bit&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Data.Set d:83F98010 %l 0x01&lt;/P&gt;&lt;P&gt;//Set PROGD in STAT&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Data.Set d:83F98000 %l 0x02&lt;/P&gt;&lt;P&gt;////////////////////////third bit is 0!&lt;/P&gt;&lt;P&gt;After I will execute it&amp;nbsp; FB0REG1 = 0x60 &lt;SPAN lang="en"&gt;&lt;SPAN class="hps"&gt;but when I&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;reset the&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;cpu&lt;/SPAN&gt; FUSE &lt;SPAN class="hps"&gt;back&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;to the default value = 00.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="short_text" lang="en"&gt;&lt;SPAN class="short_text" lang="en"&gt;&lt;SPAN class="alt-edited hps"&gt;It is not important&lt;/SPAN&gt;&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;how&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;the imx boot moode (Internal Boot / Internal Boot-ROM Selected)&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Mayby I don't understand algorytm.&lt;/P&gt;&lt;P&gt;Can anyone can help my?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Lukas.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 30 Jul 2013 13:11:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX515-Fuze-Bits/m-p/230033#M17110</guid>
      <dc:creator>wysockilukasz</dc:creator>
      <dc:date>2013-07-30T13:11:02Z</dc:date>
    </item>
    <item>
      <title>Re: IMX515 Fuze Bits</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX515-Fuze-Bits/m-p/230034#M17111</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Problem solved!&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="en"&gt;&lt;SPAN class="hps"&gt;The algorithm&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;above&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;is correct&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;but I&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;also&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;need to set the&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;bit:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;efuse_prog_supply_gate (CGPR -&amp;gt; 0x73FD_4064),&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="en"&gt;&lt;SPAN class="hps"&gt;(and&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;additional information&lt;/SPAN&gt;&lt;SPAN&gt;, you must&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;have a&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;3.3 V&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;on pin&lt;/SPAN&gt; &lt;SPAN class="hps"&gt;VDD_FUSE).&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="en"&gt;&lt;SPAN class="hps"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="en"&gt;&lt;SPAN class="hps"&gt;Lukas.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 01 Aug 2013 09:47:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX515-Fuze-Bits/m-p/230034#M17111</guid>
      <dc:creator>wysockilukasz</dc:creator>
      <dc:date>2013-08-01T09:47:50Z</dc:date>
    </item>
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