PCIe Endpoint Doorbell or Interrupt

carlpii — Fri, 29 Jan 2016 17:43:13 GMT

It is common for a PCIe add-in card to have a "doorbell" register or similar functionality (eg, a queue tail pointer) that the host system can write to start an I/O operation. I haven't found a way to trigger an ARM interrupt as a result of an inbound PCIe write transaction with the i.MX6 operating in endpoint mode. I'm currently stuck polling on memory locations which is a really ugly solution. Is there a way to implement this type of behavior that doesn't rely on polling?

Thanks,

-Carl

Re: PCIe Endpoint Doorbell or Interrupt

Yuri — Mon, 01 Mar 2021 10:14:45 GMT

Hello,

The following discussion - hope - helps.

https://community.nxp.com/t5/i-MX-Processors/Endpoint-Interrupt-via-PCIe/m-p/250595

Regards,
Yuri.

topic Re: PCIe Endpoint Doorbell or Interrupt in i.MX Processors

PCIe Endpoint Doorbell or Interrupt

Re: PCIe Endpoint Doorbell or Interrupt