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    <title>i.MX ProcessorsのトピックRe: CONFIG_NR_DRAM_BANKS=8?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/CONFIG-NR-DRAM-BANKS-8/m-p/1230146#M169412</link>
    <description>&lt;P&gt;Thank you for the quick response.&lt;/P&gt;&lt;P&gt;This makes sense now, and it all lines up with my application purposes.&lt;/P&gt;&lt;P&gt;Thanks a lot &lt;LI-EMOJI id="lia_slightly-smiling-face" title=":slightly_smiling_face:"&gt;&lt;/LI-EMOJI&gt;&lt;/P&gt;</description>
    <pubDate>Fri, 12 Feb 2021 02:30:16 GMT</pubDate>
    <dc:creator>IHGG</dc:creator>
    <dc:date>2021-02-12T02:30:16Z</dc:date>
    <item>
      <title>CONFIG_NR_DRAM_BANKS=8?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/CONFIG-NR-DRAM-BANKS-8/m-p/1229629#M169346</link>
      <description>&lt;P&gt;Hi there. After using an evaluation kit with the i.MX8QXP, the U-Boot defconfig file contained CONFIG_NR_DRAM_BANKS=3. (Number of DRAM banks)&lt;/P&gt;&lt;P&gt;I am wondering why it is 3 in this case. The DRAM chip used was MT53B768M32D4DT-062.&lt;/P&gt;&lt;P&gt;Now I am working with a custom board using a&amp;nbsp;MT41K256M16TW-107 IT:P DDR3L SDRAM chip and there is a lot more information available about it. I suspect that the number of DRAM banks should set to be 8 (according to the datasheet), but am not 100% sure.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;There is a very similar question already out there by&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/46946"&gt;@soujanyak&lt;/a&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Enabling-4-Gb-in-uboot-build-for-i-MX6Q/m-p/292704#M35916" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/Enabling-4-Gb-in-uboot-build-for-i-MX6Q/m-p/292704#M35916&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any help would be greatly appreciated &lt;LI-EMOJI id="lia_slightly-smiling-face" title=":slightly_smiling_face:"&gt;&lt;/LI-EMOJI&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;</description>
      <pubDate>Thu, 11 Feb 2021 02:01:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/CONFIG-NR-DRAM-BANKS-8/m-p/1229629#M169346</guid>
      <dc:creator>IHGG</dc:creator>
      <dc:date>2021-02-11T02:01:26Z</dc:date>
    </item>
    <item>
      <title>Re: CONFIG_NR_DRAM_BANKS=8?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/CONFIG-NR-DRAM-BANKS-8/m-p/1229646#M169349</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/183371"&gt;@IHGG&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; here&amp;nbsp;&lt;SPAN&gt;CONFIG_NR_DRAM_BANKS is number of bits: 2 ** 3 = 8&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Thu, 11 Feb 2021 04:28:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/CONFIG-NR-DRAM-BANKS-8/m-p/1229646#M169349</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2021-02-11T04:28:54Z</dc:date>
    </item>
    <item>
      <title>Re: CONFIG_NR_DRAM_BANKS=8?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/CONFIG-NR-DRAM-BANKS-8/m-p/1230146#M169412</link>
      <description>&lt;P&gt;Thank you for the quick response.&lt;/P&gt;&lt;P&gt;This makes sense now, and it all lines up with my application purposes.&lt;/P&gt;&lt;P&gt;Thanks a lot &lt;LI-EMOJI id="lia_slightly-smiling-face" title=":slightly_smiling_face:"&gt;&lt;/LI-EMOJI&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 12 Feb 2021 02:30:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/CONFIG-NR-DRAM-BANKS-8/m-p/1230146#M169412</guid>
      <dc:creator>IHGG</dc:creator>
      <dc:date>2021-02-12T02:30:16Z</dc:date>
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