<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: About Table 6-50 (Quad SPI configuration parameters) of i.MX 7 Dual Reference Manual in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/About-Table-6-50-Quad-SPI-configuration-parameters-of-i-MX-7/m-p/1230105#M169409</link>
    <description>&lt;P&gt;hello,&lt;/P&gt;&lt;P&gt;I haven't received an answer back, so I'll change the question.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Is the correspondence of the QSPI_SMPR [DDRSMP] register for Full Speed Phase Selection and Full Speed Delay Selection (Table 6-50 in the Reference Manual) in DDR mode as follows?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Full Speed Phase Selection | 0 | 1 | 0 | 1&lt;BR /&gt;________________________________________________________&lt;/P&gt;&lt;P&gt;Full Speed Delay Selection | 0 | 0 | 1 | 1&lt;BR /&gt;=====================================================&lt;BR /&gt;QSPI_SMPR [DDRSMP]&amp;nbsp; &amp;nbsp; | 0 | 1 | 2 | 3&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Goto&lt;/P&gt;</description>
    <pubDate>Fri, 12 Feb 2021 00:08:43 GMT</pubDate>
    <dc:creator>goto11</dc:creator>
    <dc:date>2021-02-12T00:08:43Z</dc:date>
    <item>
      <title>About Table 6-50 (Quad SPI configuration parameters) of i.MX 7 Dual Reference Manual</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Table-6-50-Quad-SPI-configuration-parameters-of-i-MX-7/m-p/1227931#M169145</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hello,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;For the settings of Full Speed Phase Selection and Full Speed Delay Selection, is the value of QuadSPIx_SMPR [DDRSMP] updated in DDR mode?&lt;/P&gt;&lt;P&gt;How many QuadSPIx_SMPR [DDRSMP] do you support for each of the examples below?&lt;BR /&gt;Example 1&lt;BR /&gt;Full Speed Phase Selection: 0&lt;BR /&gt;Full Speed Delay Selection: 1&lt;BR /&gt;Example 2&lt;BR /&gt;Full Speed Phase Selection: 1&lt;BR /&gt;Full Speed Delay Selection: 0&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;best regards&lt;BR /&gt;Goto&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 08 Feb 2021 11:44:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Table-6-50-Quad-SPI-configuration-parameters-of-i-MX-7/m-p/1227931#M169145</guid>
      <dc:creator>goto11</dc:creator>
      <dc:date>2021-02-08T11:44:47Z</dc:date>
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    <item>
      <title>Re: About Table 6-50 (Quad SPI configuration parameters) of i.MX 7 Dual Reference Manual</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Table-6-50-Quad-SPI-configuration-parameters-of-i-MX-7/m-p/1228226#M169169</link>
      <description>&lt;P&gt;Hi Goto,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The first question is yes.&lt;/P&gt;
&lt;P&gt;And for the second question, it just supports two modes for each example.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Hope this helps you.&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Israel H.&lt;/P&gt;</description>
      <pubDate>Mon, 08 Feb 2021 20:41:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Table-6-50-Quad-SPI-configuration-parameters-of-i-MX-7/m-p/1228226#M169169</guid>
      <dc:creator>nxf63675</dc:creator>
      <dc:date>2021-02-08T20:41:49Z</dc:date>
    </item>
    <item>
      <title>Re: About Table 6-50 (Quad SPI configuration parameters) of i.MX 7 Dual Reference Manual</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Table-6-50-Quad-SPI-configuration-parameters-of-i-MX-7/m-p/1228320#M169182</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;Please tell me the correspondence between Full Speed Phase Selection and Full Speed Delay Selection with QSPI_SMPR [DDRSMP].&lt;BR /&gt;As an example, please tell us about two cases.&lt;BR /&gt;What is QSPI_SMPR [DDRSMP] set when Full Speed Phase Selection is "1" and Full Speed Delay Selection is "0"?&lt;BR /&gt;What is QSPI_SMPR [DDRSMP] set when Full Speed Phase Selection is "1" and Full Speed Delay Selection"1"?&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Goto&lt;/P&gt;</description>
      <pubDate>Thu, 11 Feb 2021 05:19:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Table-6-50-Quad-SPI-configuration-parameters-of-i-MX-7/m-p/1228320#M169182</guid>
      <dc:creator>goto11</dc:creator>
      <dc:date>2021-02-11T05:19:59Z</dc:date>
    </item>
    <item>
      <title>Re: About Table 6-50 (Quad SPI configuration parameters) of i.MX 7 Dual Reference Manual</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Table-6-50-Quad-SPI-configuration-parameters-of-i-MX-7/m-p/1230105#M169409</link>
      <description>&lt;P&gt;hello,&lt;/P&gt;&lt;P&gt;I haven't received an answer back, so I'll change the question.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Is the correspondence of the QSPI_SMPR [DDRSMP] register for Full Speed Phase Selection and Full Speed Delay Selection (Table 6-50 in the Reference Manual) in DDR mode as follows?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Full Speed Phase Selection | 0 | 1 | 0 | 1&lt;BR /&gt;________________________________________________________&lt;/P&gt;&lt;P&gt;Full Speed Delay Selection | 0 | 0 | 1 | 1&lt;BR /&gt;=====================================================&lt;BR /&gt;QSPI_SMPR [DDRSMP]&amp;nbsp; &amp;nbsp; | 0 | 1 | 2 | 3&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Goto&lt;/P&gt;</description>
      <pubDate>Fri, 12 Feb 2021 00:08:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Table-6-50-Quad-SPI-configuration-parameters-of-i-MX-7/m-p/1230105#M169409</guid>
      <dc:creator>goto11</dc:creator>
      <dc:date>2021-02-12T00:08:43Z</dc:date>
    </item>
  </channel>
</rss>

