topic Re: OpenOCD Problem i.MX6 in i.MX Processors

OpenOCD Problem i.MX6

matthiasniederm — Mon, 18 Mar 2013 14:25:43 GMT

Hello,

i have a "SABRE Board for Smart Devices Based on the i.MX 6 Series". And I tried to get OpenOCD to work with it.

This is my OpenOCD configuration file for the i.MX6.

# Freescale i.MX6 series single/dual/quad core processor

if { [info exists CHIPNAME] } {

set _CHIPNAME $CHIPNAME

} else {

set _CHIPNAME imx6

}

# CoreSight Debug Access Port

if { [info exists DAP_TAPID] } {

set _DAP_TAPID $DAP_TAPID

} else {

set _DAP_TAPID 0x4ba00477

}

jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \

-expected-id $_DAP_TAPID

# SDMA / no IDCODE

jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f

# System JTAG Controller

if { [info exists SJC_TAPID] } {

set _SJC_TAPID SJC_TAPID

} else {

set _SJC_TAPID 0x0191c01d

}

set _SJC_TAPID2 0x2191c01d

jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \

-expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2

# GDB target: Cortex-A9, using DAP, configuring only one core

# Base addresses of cores:

# core 0 - 0x82150000

# core 1 - 0x82152000

# core 2 - 0x82154000

# core 3 - 0x82156000

set _TARGETNAME $_CHIPNAME.cpu.0

target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \

-coreid 0 -dbgbase 0x82150000

# some TCK cycles are required to activate the DEBUG power domain

jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"

proc imx6_dbginit {target} {

# General Cortex A8/A9 debug initialisation

cortex_a8 dbginit

}

# Slow speed to be sure it will work

jtag_rclk 1000

$_TARGETNAME configure -event reset-start { jtag_rclk 1000 }

$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"

$_TARGETNAME configure -event gdb-attach { halt }

I am using the openocd-usb-hs adapter from embedded-projects. This is the output after starting OpenOCD.

Open On-Chip Debugger 0.6.1 (2013-03-18-13:15)

Licensed under GNU GPL v2

For bug reports, read

http://openocd.sourceforge.net/doc/doxygen/bugs.html

Info : only one transport option; autoselect 'jtag'

Warn : imx6.sdma: nonstandard IR value

RCLK - adaptive

adapter speed: 3000 kHz

Info : max TCK change to: 30000 kHz

Info : clock speed 3000 kHz

Polling target failed, GDB will be halted. Polling again in 100ms

Polling target failed, GDB will be halted. Polling again in 300ms

Error: couldn't read enough bytes from FT2232 device (0 < 81)

Error: couldn't read from FT2232

in procedure 'runtest'

Error: JTAG scan chain interrogation failed: all ones

Error: Check JTAG interface, timings, target power, etc.

Error: Trying to use configured scan chain anyway...

Error: couldn't read enough bytes from FT2232 device (0 < 3)

Error: couldn't read from FT2232

Warn : Bypassing JTAG setup events due to errors

Error: couldn't read enough bytes from FT2232 device (0 < 12)

Error: couldn't read from FT2232

Polling target failed, GDB will be halted. Polling again in 700ms

Polling target failed, GDB will be halted. Polling again in 1500ms

I hope it is enough information.. If not please say what you need..

Do you have any idea what's the problem?

Thank you! I hope you can help me!

MaTT

Re: OpenOCD Problem i.MX6

matthiasniederm — Wed, 03 Apr 2013 08:09:16 GMT

Re: OpenOCD Problem i.MX6

matthiasniederm — Wed, 03 Apr 2013 13:17:46 GMT

I have "solved" the Problem! I removed the RESET wire between openocd-usb and the target board. Now i have basic jtag access.

Cheers

MaTT

Re: OpenOCD Problem i.MX6

dmitriyaleksand — Mon, 08 Jul 2013 13:14:05 GMT

Hi MaTT,

could you share your experience with OpenOCD and iMX6?

I've got the same problem but in my case it doesn't work even without RESET pin. Moreover I can't see any data on the JTAG pins with logic analizer when using imx6.cfg script. But the data is present when I change config script to stm32f103.

Regards,

Dmitriy

Re: OpenOCD Problem i.MX6

rp123 — Fri, 09 Aug 2013 18:22:02 GMT

Can you share your board config file? I am having trouble setting up the DCD settings to R/W from SDRAM

Re: OpenOCD Problem i.MX6

douglasbolton — Tue, 01 Apr 2014 02:47:56 GMT

I have issues with OpenOcd and the i.mx6. I have removed the reset line from the JTAG adapter and I get basic JTAG functionality. My issue is when I have a new board with no software programmed when I type "halt" I get -

> halt

number of cache level 1

imx6.cpu.0 cluster 0 core 0 multi core

target state: halted

target halted in Thumb state due to debug-request, current mode: Supervisor

cpsr: 0x600001f3 pc: 0x00000fc4

MMU: disabled, D-Cache: disabled, I-Cache: disabled

Where the processor always halts in thumb mode.

Has anyone overcome this issue and has the correct reset setup for the openocd config files so that the target is halted in arm mode ?

If I have programmed u-boot into flash the processor will halt correctly in arm mode. However I need the board to halt correctly before u-boot is programmed.

Thanks

Doug.

Re: OpenOCD Problem i.MX6

fatalfeel — Tue, 08 Dec 2015 08:12:27 GMT

Sharing debug i.mx6 from uboot to kernel to jni with Eclipse

////////////////////host ubuntu terminal

root@stonelinux:/opt/openocd/bin# ./openocd -f /opt/openocd/share/openocd/scripts/interface/ftdi/dp_busblaster.cfg -f /opt/openocd/share/openocd/scripts/target/imx6.cfg

Open On-Chip Debugger 0.8.0 (2015-11-27-10:25)

Licensed under GNU GPL v2

For bug reports, read

http://openocd.sourceforge.net/doc/doxygen/bugs.html

Info : only one transport option; autoselect 'jtag'

Warn : imx6.sdma: nonstandard IR value

adapter speed: 1000 kHz

Info : clock speed 1000 kHz

Info : JTAG tap: imx6.dap tap/device found: 0x4ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x4)

Info : TAP imx6.sdma does not have IDCODE

Info : JTAG tap: imx6.sjc tap/device found: 0x2191e01d (mfg: 0x00e, part: 0x191e, ver: 0x2)

Info : imx6.cpu.0: hardware has 6 breakpoints, 4 watchpoints

Info : accepting 'gdb' connection from 3333

Info : number of cache level 1

Info : imx6.cpu.0 cluster 0 core 0 multi core

target state: halted

target halted in ARM state due to debug-request, current mode: Supervisor

cpsr: 0x200001d3 pc: 0x4ff70548

MMU: enabled, D-Cache: enabled, I-Cache: enabled

/////////////////////////after target kernel startup finish will happen

Error: JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed

Error: MEM_AP_CSW 0x24770002, MEM_AP_TAR 0x24770002

Error: JTAG-DP OVERRUN - check clock, memaccess, or reduce jtag speed

Error: MEM_AP_CSW 0x24770002, MEM_AP_TAR 0x24770002

Warn : Timeout (1000ms) waiting for ACK=OK/FAULT in JTAG-DP transaction - aborting

Polling target imx6.cpu.0 failed, GDB will be halted. Polling again in 100ms

Warn : target imx6.cpu.0 is not halted

Error: Target not halted

//////////////////////solved by this way

gedit /root/project_board/free_imx/myandroid/kernel_imx/arch/arm/configs/mx6dq_android_defconfig

CONFIG_CPU_IDLE=y

#CONFIG_CPU_IDLE=y

gedit /root/project_board/free_imx/myandroid/kernel_imx/arch/arm/mach-imx/pm-imx6.c

val |= 0x1 << BP_CLPCR_LPM;

val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;

/*val |= 0x1 << BP_CLPCR_LPM;

val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;*/

rebuild kernel and upload to target i.mx6 board

It because CPU_IDLE low power mode will close jtag function

if want to know more way read

Debugging Linux Kernel over JTAG with J-Link

/////

//i.mx6 only have hardware breakpoint.

//Could not insert single-step breakpoint, cannot continue bug fixed

search in gdb_server.c

if (type == 0) /* memory breakpoint */

bp_type = BKPT_SOFT;

modify to

bp_type = BKPT_HARD;

//add support for openpocd

$_TARGETNAME configure -event reset-assert "imx6q_init"

$_TARGETNAME configure -event reset-end "clear_regs"

http://wiki.voipac.com/xwiki/bin/view/imx6+rex/jtag_oocd