<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックInput timing in DDR mode with loopback DQS sampling</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Input-timing-in-DDR-mode-with-loopback-DQS-sampling/m-p/1228447#M169192</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have two questions about QuadSPI's Input timing in DDR mode with loopback DQS sampling.&lt;BR /&gt;No1&lt;BR /&gt;Is it a mode that can be used with serial flash without DQS?&lt;BR /&gt;No2&lt;BR /&gt;Can the QSPI_A_DQS (EPDC1_DATA04) pin be open when used in this mode?&lt;BR /&gt;Or does the QSPI_A_DQS (EPDC1_DATA04) pin connect to any pin?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Goto&lt;/P&gt;</description>
    <pubDate>Tue, 09 Feb 2021 03:52:21 GMT</pubDate>
    <dc:creator>goto11</dc:creator>
    <dc:date>2021-02-09T03:52:21Z</dc:date>
    <item>
      <title>Input timing in DDR mode with loopback DQS sampling</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Input-timing-in-DDR-mode-with-loopback-DQS-sampling/m-p/1228447#M169192</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have two questions about QuadSPI's Input timing in DDR mode with loopback DQS sampling.&lt;BR /&gt;No1&lt;BR /&gt;Is it a mode that can be used with serial flash without DQS?&lt;BR /&gt;No2&lt;BR /&gt;Can the QSPI_A_DQS (EPDC1_DATA04) pin be open when used in this mode?&lt;BR /&gt;Or does the QSPI_A_DQS (EPDC1_DATA04) pin connect to any pin?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Goto&lt;/P&gt;</description>
      <pubDate>Tue, 09 Feb 2021 03:52:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Input-timing-in-DDR-mode-with-loopback-DQS-sampling/m-p/1228447#M169192</guid>
      <dc:creator>goto11</dc:creator>
      <dc:date>2021-02-09T03:52:21Z</dc:date>
    </item>
    <item>
      <title>Re: Input timing in DDR mode with loopback DQS sampling</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Input-timing-in-DDR-mode-with-loopback-DQS-sampling/m-p/1228493#M169200</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/172587"&gt;@goto11&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp; It is possible to use DDR QSPI flash without DQS, assuming &lt;BR /&gt;the loopback. Add 18pf on the DQS pin.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Tue, 09 Feb 2021 04:27:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Input-timing-in-DDR-mode-with-loopback-DQS-sampling/m-p/1228493#M169200</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2021-02-09T04:27:04Z</dc:date>
    </item>
  </channel>
</rss>

