https://community.nxp.com/t5/i-MX-Processors/How-we-can-invalidation-the-Power-saving-state-in-PCIe-Gen1/m-p/1208862#M167468 <P>Hi Toshihiro ,</P> <P>&nbsp;&nbsp; <SPAN class="VIiyi"><SPAN class="JLqJ4b ChMk0b" data-language-for-alternatives="en" data-language-to-translate-into="zh-CN" data-phrase-index="0"><SPAN>L1 &amp; L0s are not related to GEN1/GEN2. For PCIE, as long as RC and EP support it, it can be enabled.</SPAN></SPAN></SPAN></P> <P>Have a nice day!</P> <P>B.R,</P> <P>weidong</P> Fri, 08 Jan 2021 09:53:30 GMT weidong_sun 2021-01-08T09:53:30Z https://community.nxp.com/t5/i-MX-Processors/How-we-can-invalidation-the-Power-saving-state-in-PCIe-Gen1/m-p/1208018#M167392 <P>Hi community</P><P>I am using a custom board that design based on NXP i.MX6Q sabreauto board,<BR />and we need to run PCIe device on our custom board.</P><P>We must use Yocto Sumo(linux kernel 4.14.78) environment.<BR />We would like to invalidation the Power saving state of PCIe(L0s,L1).</P><P>How we can invalidation the Power saving state(not transition from L0) in PCIe Gen1?</P><P>Best regards,<BR />Toshihiro Kambe</P> Thu, 07 Jan 2021 05:41:21 GMT https://community.nxp.com/t5/i-MX-Processors/How-we-can-invalidation-the-Power-saving-state-in-PCIe-Gen1/m-p/1208018#M167392 toshihiro_kambe 2021-01-07T05:41:21Z https://community.nxp.com/t5/i-MX-Processors/How-we-can-invalidation-the-Power-saving-state-in-PCIe-Gen1/m-p/1208862#M167468 <P>Hi Toshihiro ,</P> <P>&nbsp;&nbsp; <SPAN class="VIiyi"><SPAN class="JLqJ4b ChMk0b" data-language-for-alternatives="en" data-language-to-translate-into="zh-CN" data-phrase-index="0"><SPAN>L1 &amp; L0s are not related to GEN1/GEN2. For PCIE, as long as RC and EP support it, it can be enabled.</SPAN></SPAN></SPAN></P> <P>Have a nice day!</P> <P>B.R,</P> <P>weidong</P> Fri, 08 Jan 2021 09:53:30 GMT https://community.nxp.com/t5/i-MX-Processors/How-we-can-invalidation-the-Power-saving-state-in-PCIe-Gen1/m-p/1208862#M167468 weidong_sun 2021-01-08T09:53:30Z