i.MX8MM Skew Definiton for All High Speed Interfaces

EErdem — Thu, 31 Dec 2020 10:11:38 GMT

Hello,

I am designing SoM Module using i.MX8MM SoC

I have listed my questions below.

Q1: I am using gigabit ethernet PHY and I would like to know that what is the allowed skew parameter between RGMII data clock MDC and MDIO pins.

Q2: What is the allowed skew between MIPI DSI/CSI clock and data pins.

Q3: What is the allowed skew between SDIO Data Clock and CMP pins

Q4: What is the allowed skew between PCIe data and clock interfaces.

Thank you.

Re: i.MX8MM Skew Definiton for All High Speed Interfaces

igorpadykov — Sat, 02 Jan 2021 00:50:14 GMT

Hi EErdem

peripheral timings can be found in datasheet :

Best regards
igor