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    <title>i.MX ProcessorsのトピックRe: 8MMINID4 Reference Design + eMMC boot issue</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192806#M165902</link>
    <description>&lt;P&gt;In the software the uSDHC3 clock is not initialized in default. We must let CONFIG_SYS_FSL_USDHC_NUM=2 to run the uSDHC3 clock initialization code. How to add you can refer to the thread by my colleague.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Enabling-uSDHC1-of-i-MX8MM-Based-On-L5-4-24-2-1-0-BSP/ta-p/1190668" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Enabling-uSDHC1-of-i-MX8MM-Based-On-L5-4-24-2-1-0-BSP/ta-p/1190668&lt;/A&gt;&lt;/P&gt;</description>
    <pubDate>Thu, 03 Dec 2020 03:37:05 GMT</pubDate>
    <dc:creator>Rita_Wang</dc:creator>
    <dc:date>2020-12-03T03:37:05Z</dc:date>
    <item>
      <title>8MMINID4 Reference Design + eMMC boot issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192239#M165855</link>
      <description>&lt;P&gt;Hi Supporter,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;We follow&amp;nbsp;8MMINID4 to design a new HW and replace NAND to eMMC as below.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="KennyChu_2-1606902331512.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/131545iB20F3D29D147E008/image-size/medium?v=v2&amp;amp;px=400" role="button" title="KennyChu_2-1606902331512.png" alt="KennyChu_2-1606902331512.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="KennyChu_3-1606902417471.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/131546i2B5BDF060C15599A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="KennyChu_3-1606902417471.png" alt="KennyChu_3-1606902417471.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;We can update image successfully by using UUU tool. Please check UUU log and uuu.auto for command list.&lt;/P&gt;&lt;P&gt;After reboot, it will hang up at u-boot and complain "MMC Device 1 not found".&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can you help to check and advise?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;boot up log:&lt;/P&gt;&lt;P&gt;&lt;EM&gt;U-Boot SPL 2019.04-lf-5.4.y_v2019.04+g48508669 (Dec 02 2020 - 02:47:35 +0000)&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;power_pca9450_init&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;DDRINFO: start DRAM init&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;Training FAILED&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;DDRINFO:ddrphy calibration done&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;DDRINFO: ddrmix config done&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;Normal Boot&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;Trying to boot from MMC2&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;FONT color="#FF0000"&gt;MMC Device 1 not found&lt;/FONT&gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;spl: could not find mmc device 1. error: -19&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;SPL: failed to boot from all boot devices&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;In U-boot prompt, we can found eMMC device at port2.&lt;/P&gt;&lt;P&gt;log:&lt;/P&gt;&lt;P&gt;&lt;EM&gt;u-boot=&amp;gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;u-boot=&amp;gt; mmc list&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;FSL_SDHC: 2&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;u-boot=&amp;gt; mmc dev 1&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;MMC Device 1 not found&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;no mmc device at slot 1&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;FONT color="#FF0000"&gt;u-boot=&amp;gt; mmc dev 2&lt;/FONT&gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;FONT color="#FF0000"&gt;switch to partitions #0, OK&lt;/FONT&gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;FONT color="#FF0000"&gt;mmc2(part 0) is current device&lt;/FONT&gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;u-boot=&amp;gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Kenny&lt;/P&gt;</description>
      <pubDate>Wed, 02 Dec 2020 09:56:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192239#M165855</guid>
      <dc:creator>KennyChu</dc:creator>
      <dc:date>2020-12-02T09:56:08Z</dc:date>
    </item>
    <item>
      <title>Re: 8MMINID4 Reference Design + eMMC boot issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192251#M165858</link>
      <description>&lt;P&gt;Which uSDHC are you using for emmc? uSDHC1?&lt;/P&gt;</description>
      <pubDate>Wed, 02 Dec 2020 10:26:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192251#M165858</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2020-12-02T10:26:22Z</dc:date>
    </item>
    <item>
      <title>Re: 8MMINID4 Reference Design + eMMC boot issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192255#M165859</link>
      <description>&lt;P&gt;We are using&amp;nbsp;uSDHC3. You can check ROM Fuse map below.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="KennyChu_1-1606905019617.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/131549i904ECE874AD91F5C/image-size/medium?v=v2&amp;amp;px=400" role="button" title="KennyChu_1-1606905019617.png" alt="KennyChu_1-1606905019617.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 02 Dec 2020 10:30:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192255#M165859</guid>
      <dc:creator>KennyChu</dc:creator>
      <dc:date>2020-12-02T10:30:35Z</dc:date>
    </item>
    <item>
      <title>Re: 8MMINID4 Reference Design + eMMC boot issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192793#M165901</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/57740"&gt;@Rita_Wang&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any update?&lt;/P&gt;</description>
      <pubDate>Thu, 03 Dec 2020 03:19:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192793#M165901</guid>
      <dc:creator>KennyChu</dc:creator>
      <dc:date>2020-12-03T03:19:05Z</dc:date>
    </item>
    <item>
      <title>Re: 8MMINID4 Reference Design + eMMC boot issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192806#M165902</link>
      <description>&lt;P&gt;In the software the uSDHC3 clock is not initialized in default. We must let CONFIG_SYS_FSL_USDHC_NUM=2 to run the uSDHC3 clock initialization code. How to add you can refer to the thread by my colleague.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Enabling-uSDHC1-of-i-MX8MM-Based-On-L5-4-24-2-1-0-BSP/ta-p/1190668" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Enabling-uSDHC1-of-i-MX8MM-Based-On-L5-4-24-2-1-0-BSP/ta-p/1190668&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 03 Dec 2020 03:37:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192806#M165902</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2020-12-03T03:37:05Z</dc:date>
    </item>
    <item>
      <title>Re: 8MMINID4 Reference Design + eMMC boot issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192843#M165906</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/57740"&gt;@Rita_Wang&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks a lot. It can enter kernel now.&lt;/P&gt;</description>
      <pubDate>Thu, 03 Dec 2020 04:56:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192843#M165906</guid>
      <dc:creator>KennyChu</dc:creator>
      <dc:date>2020-12-03T04:56:34Z</dc:date>
    </item>
    <item>
      <title>Re: 8MMINID4 Reference Design + eMMC boot issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192883#M165909</link>
      <description>&lt;P&gt;Good news it works now.&lt;/P&gt;</description>
      <pubDate>Thu, 03 Dec 2020 06:04:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/8MMINID4-Reference-Design-eMMC-boot-issue/m-p/1192883#M165909</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2020-12-03T06:04:58Z</dc:date>
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