topic Re: UART pins condition during power on reset in i.MX Processors

UART pins condition during power on reset

YusukeHirai — Wed, 25 Nov 2020 04:13:55 GMT

Hi,

I am trying to use two CPUs and let them communicate with UART.
(One is MCIMX6Y2CVM08AB, and the other is other manufacturers.)

I was worried about whether both signals were output for the power-on reset condition .

It was confirmed that the cpu of other manufacturers became hi-z and there was no problem.
But I didn't understand the operation of IMX6.
So I have a question about this.

There is a description out of reset condition in the IMX6's data sheet.
However, there is no description of reset condition.
Does anyone know?

The IMX6 uses the following pins
GPIO3_IO0 (LCD_CLK)
GPIO_IO1 (LCD_ENABLE)

Please let me know if anyone knows.

Regards,

Yusuke

Re: UART pins condition during power on reset

Yuri — Wed, 25 Nov 2020 06:32:43 GMT

@YusukeHirai
Hello,

During power up sequence and short period of stabilization, also during reset,
i.MX 6ULL pin states are not pre-defined.

Regards,
Yuri.

Re: UART pins condition during power on reset

ban45 — Wed, 25 Nov 2020 06:57:46 GMT

Hello

If the connected device is an output, will it conflict?

Is it high impedance during reset?

best regard

Re: UART pins condition during power on reset

Yuri — Thu, 26 Nov 2020 04:26:25 GMT

@ban45
Hello,

During power on sequence and reset - conflicts are possible.

Regards,
Yuri.

Re: UART pins condition during power on reset

ban45 — Thu, 26 Nov 2020 04:43:02 GMT

Hello,

What should I do if I connect another CPU via UART communication?

Other companies' CPUs have high impedance or input during reset.(At power-on reset)

Is there any output during the reset?
In that case, you will break the device that is OUTPUT in the connected device.
Could you please tell me how to connect the output pin to the GPIO pin?

best regard

Re: UART pins condition during power on reset

Yuri — Thu, 26 Nov 2020 05:16:18 GMT

@ban45

Reliable solution - using buffers.

~Yuri.

Re: UART pins condition during power on reset

ban45 — Thu, 26 Nov 2020 05:31:27 GMT

Hello

Is it the same for memory related such as DDR3?

Is it necessary to buffer everything if the other party is output?

best regard

Re: UART pins condition during power on reset

Yuri — Thu, 26 Nov 2020 07:46:53 GMT

@ban45
Hello,

Follow i.MX 6ULL reference design - at least - it has been tested.

Also, from section 4.2.3 (Power Supplies Usage) of i.MX 6ULL Datasheet for Consumer Products
( Rev. 1.3, 08/2018):
All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF.

Regards,
Yuri.