topic Re: The Boot / Debug Relevant Questions About Hardware Design Of I.MX8X in i.MX Processors

The Boot / Debug Relevant Questions About Hardware Design Of I.MX8X

alighieri — Fri, 20 Nov 2020 08:16:21 GMT

Hope Someone Can Help To Figure Out Following Questions For Some Hardware Design Problems Which Are Relevant For Boot / Debug.

First After Looking Upon Full Pages Of Application Processor Reference Manual I Find No UART Console Description For DDR Calibration / Boot Command Use. My Questions Are:

1. Here Should Be 1 UART Dedicated To The Purpose Of UART Console Then Developer Can Link The Designed Board Back To PC For Running DDR Calibration Tool And Stress Test And Booting Command. But I.m Not Sure Which UART Can Be Assigned For That.

2. For Video In Here Are 2 Kinds Of Interface: MIPI-CSI 2 For Primary Camera In And 8/10 Bit Parallel RGB For Secondary Parallel Camera In. No Doubt 8 / 10 Bit Could Be General RGB / BT.656. But Here Is No Descriptions About Frame Sync Supportability In Manual At All. Does Both Of 2 Camera Ports Mentioned Above Support For F-Sync?

3. Remain Video In Question. What Kind Of Color / Video Formats Are Supported? For Example I May Apply FPD-LINK Camera Link / FPD-LINK Display Link. And Both Of Them Are Designed Intended For Different Use Cases. So Even They Both Have MIPI-CSI Transmitter To Interface With I.MX8X The Incoming Video Format Would Be Different. So Here Should I Watch Out And Confirm Some Design Limitation To Prevent The Mistake.

Re: The Boot / Debug Relevant Questions About Hardware Design Of I.MX8X

igorpadykov — Fri, 20 Nov 2020 09:52:58 GMT

Hi alighieri

1. for uart configuration one can look at sect."Configuring for different UART ports"

MX8X_DDR_Tools_quickstart_guide.pdf included in ddr test package

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8-8X-Family-DDR-Tools-Release/ta-p/1121519

2. sync signals, like CSI_HSYNC, CSI_VSYNC can be found in Table 9-2. Pin Assignments

i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual

Frame signal is better described in i.MX6UL Reference Manual (the same CSI module) Chapter 19 Figure 19-1

i.MX 6UltraLite Applications Processor Reference Manual

3. supported formats are described in sect.15.1.2.4 Parallel Capture Subsystem :
" The formats supported are RGB, RAW and YUV 422.",
and Table 15-1 shows MIPI CSI formats.

Best regards
igor

Re: The Boot / Debug Relevant Questions About Hardware Design Of I.MX8X

alighieri — Fri, 20 Nov 2020 10:13:37 GMT

@igorpadykov

Where Is What You Mentioned Section About The Topic Of "Configuring For Different UART Ports"? And As I Know DDR Calibration And Boot Configuration Should Be Done By SCU. So I Guess The UART Console Only Support To Be Assigned For SCU?

Re: The Boot / Debug Relevant Questions About Hardware Design Of I.MX8X

igorpadykov — Fri, 20 Nov 2020 10:46:07 GMT

https://community.nxp.com/t5/i-MX-Processors/chaning-the-Debug-port-i-MX8QXP/m-p/886302

Re: The Boot / Debug Relevant Questions About Hardware Design Of I.MX8X

alighieri — Fri, 20 Nov 2020 11:32:00 GMT

@igorpadykov Thanks For Your Quick Response And Kindly Helps To Reply My Questions.

My Final Question Is That Only UART 3 LPUART Can Be Set Up For Boot Configuration And As Console For IOMux / DDR Calibration? I See According To Datasheet Page 4 SCU Is Only One UART Dedicated For Specific Purpose. Does The Specific Purpose Mean IOMux And Console?

And According The Discussion: That You Referred To Me They Would Like To Set Up UART 3 Instead Of Using Default UART0 That Applied In Evaluation Board. Does That Mean In MEK Board SCU UART Is Not Used But UART 0 Through SCFW API For Doing IOMux And Being Boot Console In Connection To PC?

Re: The Boot / Debug Relevant Questions About Hardware Design Of I.MX8X

igorpadykov — Fri, 20 Nov 2020 12:19:51 GMT

p.2